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rev. 1.1 /jan. 2011 1 1gb ddr3 sdram 1gb ddr3 sdram lead-free&halogen-free (rohs compliant) h5tq1g63dfr * this document is a general product descri ption and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied.
rev. 1.1 /jan. 2011 2 revision history revision no. history page date remark 0.01 preliminary initial release - apr. 2010 preliminary 1.0 corrected features (added cwl 10) corrected idd timing added idd value added input/output capacitance corrected speed bin data corrected cwl value corrected typo at table 32 added value at table 40 corrected ac timing values 3 13 23/24 25 26 ~ 28 48 129 134 151 ~ 156 sep. 2010 1.1 corrected features (added cl 12,13) corrected idd wording (slow and fast exit) 3 23 jan. 2011
rev. 1.1 /jan. 2011 3 1. description the h5tq1g63dfr-xxx series are a 1,073,741,824-bit cm os double data rate iii (ddr3) synchronous dram, ideally suited for the main memory applicatio ns which requires large memory density and high bandwidth. hynix 1gb ddr3 sdrams offer fully synchronous operations referenced to both rising and fall- ing edges of the clock. while all ad dresses and control inputs are latche d on the rising edges of the ck (falling edges of the ck), data, data strobes and writ e data masks inputs are sampled on both rising and falling edges of it. the data paths are internally pipelin ed and 8-bit prefetched to achieve very high band- width. 1.1 device features an d ordering information 1.1.1 features * this product in complianc e with the rohs directive. ? dq power & power supply : vdd & vddq = 1.5v +/- 0.075v ? dq ground supply : vssq = ground ? fully differential clock inputs (ck, ck ) operation ? differential data strobe (dqs, dqs ) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 6, 7, 8, 9, 10, 11, 12 and 13 supported ? programmable additive latency 0, cl-1, and cl-2 supported ? programmable cas write latency (cwl) = 5, 6, 7, 8,9 and 10 ? programmable burst length 4/8 with both nibble sequential and interleave mode ? programmable pasr(partial array self-refresh) for digital consumer applications. ? programmable bl=4 supported (tccd=2clk) for digi - tal consumer applications. ? programmable zq calibration supported ? bl switch on the fly ? 8banks ? 8k refresh cycles/64ms ? jedec standard 96ball fbga(x16) ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? auto self refresh supported ? write levelization supported ? on die thermal sensor supported ? 8 bit pre-fetch
rev. 1.1 /jan. 2011 4 1.1.2 ordering information part no. power supply clock frequency max data rate interface package H5TQ1G63DFR-12C vdd/vddq=1.5 v 800mhz 1.6gbps/pin sstl-15 96ball fbga h5tq1g63dfr-11c 900mhz 1.8gbps/pin h5tq1g63dfr-n0c 1.0ghz 2.0gbps/pin
rev. 1.1 /jan. 2011 5 1.2 package ballout/m echanical dimension x16 package ball out (top view): 96 ball fbga package (no support balls) 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss a b vssq vdd vss dqsu dqu6 vssq b c vddq dqu3 dqu1 dqsu dqu2 vddq c d vssq vddq dmu dqu0 vssq vdd d e vss vssq dql0 dml vssq vddq e f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl vdd vss vssq g h vrefdq vddq dql4 dql7 dql5 vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 a15 vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 a14 a8 vss t 1 2 3 4 5 6 7 8 9 12 a b c d e f g h j k l m n populated ball ball not populated p t 3 789 (top view: see the balls through the r package)
rev. 1.1 /jan. 2011 6 1.3 row and column address table 1gb note1: page size is the number of bytes of data deliver ed from the array to the internal sense amplifiers when an active command is registered. page size is per bank, calculated as follows: page size = 2 colbits * org 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits 1.4 pin functional description configuration 64mb x 16 # of banks 8 bank address ba0 - ba2 auto precharge a10/ap bl switch on the fly a12/bc row address a0 - a12 column address a0 - a9 page size 1 2 kb symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . cke, (cke0), (cke1) input clock enable: cke high activates, and cke lo w deactivates, internal clock signals and device input buffers and output drivers. ta king cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initialization sequ ence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke, are disabled during power- down. input buffers, excluding cke, are disabled during self-refresh. cs , (cs 0), (cs 1), (cs 2), (cs 3) input chip select: all commands are masked when cs is registered high. cs provides for external rank selectio n on systems with multiple ranks. cs is considered part of the command code. odt, (odt0), (odt1) input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration, odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras . cas . we input command inputs: ras , cas and we (along with cs ) define the command being entered.
rev. 1.1 /jan. 2011 7 dm, (dmu), (dml) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines which mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-c ode during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprecha rge).a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc input burst chop: a12 / bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst choppe d). see command truth table for details. reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs , dqsu, dqsu , dqsl, dqsl input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. the data strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram supports differential da ta strobe only and does not support single-ended. nc no connect: no internal elec trical connection is present. nf no function v ddq supply dq power supply: 1.5v +/- 0.075v v ssq supply dq ground v dd supply power supply: 1.5v +/- 0.075v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage for ca zq supply reference pin for zq calibration symbol type function
rev. 1.1 /jan. 2011 8 note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function
rev. 1.1 /jan. 2011 9 2. absolute maximum ratings 2.1 absolute maximum dc ratings 3. operating conditions 3.1 dram component oper ating temperature range absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1,3 v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 o c1, 2 notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sectio ns of this specification is not implie d. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500m v; vref may be equal to or less than 300mv. temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range (optional) 85 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperat ure on the center / top side of the dram. for measure- ment conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. dur- ing operation, the dram case temperat ure must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are supported in th is range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, therefor e reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. if self-refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperat ure range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).
rev. 1.1 /jan. 2011 10 3.2 recommended dc operating conditions recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together.
rev. 1.1 /jan. 2011 11 4. idd and iddq specification parameters and test conditions 4.1 idd and iddq me asurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) ar e measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied togeth er. any iddq current is not included in idd cur- rents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied togeth er. any idd current is not included in iddq cur- rents. attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(min). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patter ns are described in table 3 through table 10. ? idd measurements are done after pr operly initializing the ddr3 sdram. this includes but is not lim- ited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ?define d = {cs , ras , cas , we }:= {high, low, low, low} ?define d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 1.1 /jan. 2011 12 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above] figure 2 - correlation from simulated channel io power to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 1.1 /jan. 2011 13 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol 800mhz 900mhz 1.0ghz unit t ck 1.25 1.1 1 ns cl 10 12 13 nck n rcd 12 14 16 nck n rc 40 46 52 nck n ras 30 34 37 nck n rp 12 14 16 nck n faw 34 38 40 nck n rrd 777nck n rfc -1 gb 88 100 110 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partially toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cycling wi th one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-read-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address, bank addres s inputs, data io: partiall y toggling according to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4. i dd2n precharge standby current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling according to ta ble 5; data io: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5.
rev. 1.1 /jan. 2011 14 i dd2nt precharge standby odt current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling according to ta ble 6; data io: mid-level; dm: stable at 0; bank activity: all banks closed; output buffe r and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i ddq2nt (optional) precharge standby odt iddq current same definition like for idd2nt, however me asuring iddq current instead of idd current i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling according to ta ble 5; data io: mid-level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid-level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0 i ddq4r (optional) operating burst read iddq current same definition like for idd4r, however measuring iddq current instead of idd current symbol description
rev. 1.1 /jan. 2011 15 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling accord ing to table 7; data io: seamless read data burst with different data between one burst and the next one according to table 7; dm: stable at 0; bank activity: all banks open, rd command s cycling through banks: 0,0,1,1,2, 2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling accord ing to table 8; data io: seamless read data burst with different data between one burst and the next one according to table 8; dm: stable at 0; bank activity: all banks open, wr comman ds cycling through banks: 0,0,1,1, 2,2,...(see table 8); output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tc k, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; com- mand, address, bank address inputs: partially toggl ing according to table 9; data io: mid-level; dm: stable at 0; bank activity: ref command every nrec (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid-level; dm: stable at 0; bank activity: self-refresh operation; out- put buffer and rtt: enabled in mode registers b) ; odt signal: mid-level i dd6et self-refresh current: extended temperature range t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extend- ed e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid-level; dm: stable at 0; bank activity: extended tempera- ture self-refresh operation; output buff er and rtt: enabled in mode registers b) ; odt signal: mid- level symbol description
rev. 1.1 /jan. 2011 16 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd6tc auto self-refresh current t case : 0 - 95 o c; auto self-refresh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: auto self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a)f) ; al: cl-1; cs : high between act and rda; command, address, ba nk address inputs: partially toggling according to table 10; data io: read data bu rst with different data between one burst and the next one according to table 10; dm: stable at 0; bank activity: two ti mes interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10; output bu ffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 1.1 /jan. 2011 17 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111 0 0000 0 f 0 - ... repeat pattern nrc+1... 4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc+1. ..4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 /jan. 2011 18 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operatio n, dq signals are mid-level ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nr as - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrcd - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,...4 until n rc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until 2* nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 /jan. 2011 19 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2nt measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-27 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 100000000 00 - 1 d 100000000 00 - 2d 111100000 f0 - 3d 111100000 f0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, bu t odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-27 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 1.1 /jan. 2011 20 table 7 - idd4r and iddq24rmeasurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operatio n, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1 d 1000000000 00 - 2,3 d ,d 1111000000 00 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5 d 1000000000 f0 - 6,7 d ,d 1111000000 f0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 1.1 /jan. 2011 21 table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write command. outside burst operation, dq signals are mid-level. table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1 d 1000100000 00 - 2,3 d ,d 1111100000 00 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5 d 1000100000 f0 - 6,7 d ,d 1111100000 f0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref000100000 00 - 11.2 d, d1000000000 00 - 3,4 d , d 1111000000 f0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 1.1 /jan. 2011 22 table 10 - idd7 measurement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operatio n, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2*nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2*nfaw+nrrd+2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100003000000- assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d100007000000- assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 1.1 /jan. 2011 23 4.2 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. i dd specification speed grade bin 800mhz 900mhz 1.0ghz unit symbol max. max. max. i dd0 60 65 70 ma i dd1 70 75 80 ma i dd2p (0) slow exit 10 10 10 ma i dd2p (1) fast exit 20 20 20 ma i dd2n 30 30 30 ma i dd2q 30 30 35 ma i dd3p (fast exit) 25 25 30 ma i dd3n 45 45 50 ma i dd4r 150 170 180 ma i dd4w 150 170 180 ma i dd5 130 150 160 ma i dd6 10 10 10 ma i dd7 200 220 240 ma
rev. 1.1 /jan. 2011 24 4.2.1 idd6tc specification symbol temperature range value unit notes 900mhz i dd6 0 - 85 o c 10 ma 2,3 i dd6et 0 - 95 o c 10 ma 4,5 i dd6tc 0 o c ~ t a 10 ma 5,6,7 1. max. values for idd currents considering worst case conditions of process, temperature and voltage. 2. applicable for mr2 settings a6=0 and a7=0 . 3. supplier data sheets include a max value for idd6 . 4. applicable for mr2 settings a6=0 and a7=1. idd6et is only specified for devices which support the extended temperature range feature . 5. refer to the supplier data sheet for the value specific ation method (e.g. max, typi cal) for idd6et and idd6tc 6. applicable for mr2 settings a6=1 and a7=0. idd6tc is only specified for devices which support the auto self refresh feature . 7. the number of discrete temperature ranges supported and th e associated ta - tz values are supplier/design specific. temperature ranges are specified for all supported valu es of toper. refer to supplier data sheet for more information.
rev. 1.1 /jan. 2011 25 5. input/output capacitance notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147( ? procedure for measuring input capacitanc e using a vector network analyzer(vna) ? ) with vdd, vddq, vss,vssq applied and all other pins floating (except the pin under test, cke, reset and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to mono lithic devices only; stacked/dual -die devices are not covered here 4. absolute value of c ck -c ck . 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras , cas , we . 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk )) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras , cas and we . 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk )) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs )) 12. maximum external load capacitance on zq pin: 5 pf. 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io 1.5 2.3 1.4 2.2 1.4 2.1 pf 1,2,3 input capacitance, ck and ck c ck 0.8 1.4 0.8 1.3 0.8 1.3 pf 2,3 input capacitance delta ck and ck c dck 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance (all other input-only pins) c i 0.75 1.3 0.75 1.2 0.75 1.2 pf 2,3,6 input capacitance delta, dqs and dqs c ddqs 0 0.15 0 0.15 0 0.15 pf 2,3,5 input capacitance delta (all ctrl input-only pins) c di_ctrl -0.4 0.2 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd -0.4 0.4 -0.4 0.4 -0.4 0.4 pf 2,3,9, 10 input/output capacitance delta (dq, dm, dqs, dqs ,tdqs, tdqs ) c dio -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin c zq - 3 - 3 - 3 pf 2,3,12
rev. 1.1 /jan. 2011 26 6. standard speed bins ddr3l sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. 800mhz speed bins speed bin 800mhz unit note parameter symbol min max internal read command to first data t aa 12.5 20 ns act to internal read or write delay time t rcd 15 - ns pre command period t rp 15 - ns act to act or ref command period t rc 50 - ns act to pre command period t ras 37.5 9*trefi ns cl = 5 cwl = 5 t ck(avg) 3 3.3 ns 1,2,3,4,8 cwl = 6, 7, 8 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7,8 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4,8 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4,8 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl=11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,8 supported cl settings 5, 6, 7, 8, 9, 10,11 n ck supported cwl settings 5, 6, 7 n ck
rev. 1.1 /jan. 2011 27 900mhz speed bins speed bin 900mhz unit note parameter symbol min max internal read command to first data t aa 13.2 20 ns act to internal read or write delay time t rcd 15.4 - ns pre command period t rp 15.4 - ns act to act or ref command period t rc 50.6 - ns act to pre command period t ras 37.4 9*trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2,3,4,9 cwl = 6, 7, 8,9 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,9 cwl = 6 t ck(avg) reserved ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,9 cwl = 7 t ck(avg) reserved ns 1,2,3,4,9 cwl = 8,9 t ck(avg) reserved ns 1,2,3,4,9 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,9 cwl = 8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 4 cl=11 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl=12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.1 1.25 ns 1,2,3,4 supported cl settings 6, 7, 8, 9, 10,11, 12 n ck supported cwl settings 5, 6, 7,8,9 n ck
rev. 1.1 /jan. 2011 28 1.0ghz speed bins speed bin 1.0ghz unit note parameter symbol min max internal read command to first data t aa 13 20 ns act to internal read or write delay time t rcd 16 - ns pre command period t rp 16 - ns act to act or ref command period t rc 52 - ns act to pre command period t ras 37 9*trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2,3,4,9 cwl = 6, 7, 8,9 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,9 cwl = 6 t ck(avg) reserved ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,9 cwl = 7 t ck(avg) reserved ns 1,2,3,4,9 cwl = 8,9 t ck(avg) reserved ns 1,2,3,4,9 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,9 cwl = 8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 4 cl=11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4,9 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl=12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.0 1.25 ns 1,2,3,4 cl=13 cwl = 5,6,7,8,9 t ck(avg) reserved ns 4 cwl = 10 t ck(avg) 0.935 1.0 ns 1,2,3,5,8 supported cl settings 6, 7, 8, 9, 10,11, 12, 13 n ck supported cwl settings 5, 6, 7,8,9,10 n ck
rev. 1.1 /jan. 2011 29 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when making a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latenc y is not purely analog - data and stro be output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck (avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3.0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck (avg) = taa.max / cl selected and round the result ing tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devi ces in the industry to support this se tting, however, it is not a mandatory feature. refer to supplier?s data sheet and spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional oper ation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional oper ation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 8. any ddr3-1600 speed bin also supports functional oper ation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 9. for devices supporting opti onal down binning to cl=7 and cl=9, taa/trcd/trpmin must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3-1333h9 devices supporting down binning to ddr3-1066g7 should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1600pb devices supporting down binning to ddr3-1333h9 or ddr3-1066g7 should program 13.125 ns in spd bytes for taamin (byte16), trcdmin (byte 18), an d trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) al so should be programmed accodingly. for example, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h9 and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600pb. 10. ddr3 800 ac timing apply if dram oper ates at lower than 800 mt/s data rate. 11. for cl5 support, refer to dimm spd in formation. dram is required to support cl5. cl5 is not mandatory in spd coding.
rev. 1.1 /jan. 2011 30 package dimensions package dimension(x16); 96ball fine pitch ball grid array outline a1 corner index area (3.250) (1.875) 7.500 0.100 13.000 0.100 0.340 0.050 1.100 0.100 top 987 321 a b c d e f g h j k l m n p r t 2.100 0.100 0.800 x 8 = 6.400 0.800 a1 ball mark 1.600 0.800 x 15 = 12.000 0.400 1.600 96 x 0.450 0.050 0.500 0.100 bottom 0.150 0.050 2-r0.130 max side 0.550 0.100 3.0 x 5.0 min flat area
rev. 1.1 /jan. 2011 31 ddr3 sdram device operation
rev. 1.1 /jan. 2011 32 contents 1. functional description 1.1 simplified state diagram 1.2 basic functionality 1.3 reset and initia lization procedure 1.3.1 power-up init ialization sequence 1.3.2 reset initializat ion with stable power 1.4 register definition 1.4.1 programming the mode registers 1.4.2 mode register mr0 1.4.3 mode register mr1 1.4.4 mode register mr2 1.4.5 mode register mr3 2. ddr3 dram command de scription and operation 2.1 command truth table 2.2 cke truth table 2.3 no operation (nop) command 2.4 deselect command 2.5 dll-off mode 2.6 dll on/off switching procedure 2.6.1 dll ?on? to dll ?off? procedure 2.6.2 dll ?off? to dll ?on? procedure 2.7 input clock frequency change 2.8 write leveling 2.8.1 dram setting for write leveling & dra m termination function in that mode 2.8.2 procedure description 2.8.3 write leveling mode exit 2.9 extended temperature usage 2.9.1 auto self-refresh mode - asr mode 2.9.2 self-refresh temperature range - srt 2.10 multi purpose register 2.10.1 mpr functional description 2.10.2 mpr register address definition 2.10.3 relevant timing parameters 2.10.4 protocol example 2.11 active command 2.12 precharge command 2.13 read operation 2.13.1 read burst operation 2.13.2 read timing definitions 2.13.3 burst read operation followed by a precharge 2.14 write operation 2.14.1 burst operation 2.14.2 write timing violations 2.14.3 write data mask
rev. 1.1 /jan. 2011 33 2.14.4 twpre calculation 2.14.5 twpst calculation 2.15 refresh command 2.16 self-refresh operation 2.17 power-down modes 2.17.1 power-down entry and exit 2.17.2 power-down clar ifications - case 1 2.17.3 power-down clar ifications - case 2 2.17.4 power-down clar ifications - case 3 2.18 zq calibration commands 2.18.1 zq calibra tions description 2.18.2 zq calibrations timing 2.18.3 zq external resistor value, tolerance, and capacitive loading 3. on-die termination (odt) 3.1 odt mode register and odt truth table 3.2 synchronous odt mode 3.2.1 odt latency and posted odt 3.2.2 timing parameters 3.2.3 odt during reads 3.3 dynamic odt 3.3.1 functional description 3.3.2 odt timing diagrams 3.4 asynchronous odt mode 3.4.1 synchronous to asynchronous odt mode transitions 3.4.2 synchronous to asynchronous odt mode transition during power-down entry 3.4.3 synchronous to asynchronous odt mode transition during power-down exit 3.4.4 synchronous to asynchronous odt mode du ring short cke high and short cke low periods 4. ac and dc input measurement levels 4.1 ac and dc logic input levels for single-ended signals 4.1.1 ac and dc input levels for single-ended command and address signals 4.1.2 ac and dc input levels for single-ended data signals 4.2 vref tolerances 4.3 ac and dc logic input leve ls for differential signals 4.3.1 differential signal definition 4.3.2 differential swing requirements for clock (ck - ck ) and strove (dqs - dqs ) 4.3.3 single-ended requirements for differential signals 4.4 differential input cross point voltage 4.5 slew rate definitions for single-ended input signals 4.6 slew rate definitions for differential input signals 5. ac and dc output measurement levels 5.1 single ended ac and dc output levels 5.2 differential ac and dc output levels 5.3 single ended output slew rate 5.4 differential output slew rate 5.5 reference load for ac timing and output slew rate
rev. 1.1 /jan. 2011 34 5.6 overshoot and undershoot specifications 5.6.1 address and control overshoo t and undershoot specifications 5.6.2 clock, data, strobe and mask overshoot and undershoot specifications 5.7 output driver dc electrical characteristics 5.7.1 output driver temperature and voltage sensitivity 5.8 on-die termination (odt) levels and i-v characteristics 5.8.1 on-die termination (odt) levels and i-v characteristics 5.8.2 odt dc electrical characteristics 5.8.3 odt temperature and voltage sensitivity 5.9 odt timing definitions 5.9.1 test load for odt timings 5.9.2 odt timing definitions 6. electrical characteristics & ac timing for 800mhz to 1.0ghz 6.1 clock specification 6.1.1 definition for tck (avg) 6.1.2 definition for tck (abs) 6.1.3 definition for tch (avg) and tcl (avg) 6.1.4 definition for tjit (per) and tjit (per, lck) 6.1.5 definition for tjit (cc) and tjit (cc, lck) 6.1.6 definition for terr (nper) 6.2 refresh parameters by device density 7. electrical characteristics and ac timing 7.1 timing parameters for 800mhz, 900mhz, and 1.0ghz speed bins 7.2 jitter notes 7.3 timing parameter notes 7.4 address / command setup, hold and derating 7.5 data setup, hold and slew rate derating
rev. 1.1 /jan. 2011 35 1. functional description 1.1 simplified state diagram this simplified state diagram is intended to provide an overview of the possible state transitions and the commands to control them. in particular, situations invo lving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. idle zq bank precharging power writing act read a read sre ref pde zqcl,zqcs pdx rdx pde write automatic sequence command sequence read a write a read pre, prea refreshing down power down active read a write a active precharge reading writing activating srx read write calibration pre, prea pre, prea write a write figure 3. simplif ied state diagram reading self refreshing mrs,mpr, write leveling zqcl initialization reset procedure power on from any state reset power applied table 11. state diagram command definitions abbreviation function abbreviation function abbreviation function act active read rd, rds4, rds8 pde enter power-down pre precharge read a rda, rdas4 , rdas8 pdx exit power-down prea precharge all write wr, wrs4, wrs8 sre self-refresh entry mrs mode register set write a wra , wras4, wras8 srx self-refresh exit ref refresh reset start reset proc edure mpr multi-purpose register zqcl zq calibration long zqc s zq calibration short - - note: see ?$paratext>? on page 50for more details. mrs
rev. 1.1 /jan. 2011 36 1.2 basic functionality read and write operation to the ddr3 sdram are burst oriented, start at a select ed location, and continue for a burst length of eight or a ?chopped? burst of four in a programmed sequence. operation begins with the registration of an active command, which is then fo llowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be activated (ba0-ba2 select the bank; a0-a15 select the row; refer to ?ddr3 sdram addressi ng? in each data sheet for specific requirements). the address bits registered coincident with the read or write command are used to select the starting column location for the burst operation, determi ne if the auto precharge command is to be issued (via a10), and select bc4 or bl8 mode ?on the fly? (via a12) if enabled in the mode register. prior to normal operation, the ddr3 sdram must be po wered up and initialized in a predefined manner. the following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. 1.3 reset and initialization procedure 1.3.1 power-up initialization sequence the following sequence is required for power up and initialization. 1. apply power (reset is recommended to be maintained below 0.2x vdd, (all other inputs may be unde- fined). reset needs to be maintained for minimum 200 us with stable power. cke is pulled ?low? any- time before reset being de-asserted (min. time 10 ns). the power voltage ramp time between 300 mv to vdd min must be no greater than 200 ms; and during the ramp, vdd>vddq and (vdd-vddq) < 0.3 volts. - vdd and vddq are driven from a single power converter output, and - the voltage levels on all pins other than vdd, vddq, vss, vssq mu st be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95 v ma x once power ramp is finished, and - vref tracks vddq/2. or - apply vdd without any slope reversal before or at the same time as vddq. - apply vddq without any slope reversal bef ore or at the same time as vtt & vref. - the voltage levels on all pins other than vdd, vddq, vss, vssq mu st be less than or equal to vddq and vdd on one side and must be large th an or equal to vssq a nd vss on the other side. 2. after reset is de-asserted, wait for another 500 us un til cke becomes active. during this time, the dram will start internal state initialization; this will be done in dependently of ex ternal clocks. 3. clocks (ck, ck ) need to be started and stabiliz ed for at least 10 ns or 5 tc k (which is larger) before cke goes active. since cke is a synchr onous signal, the corresponding set up time to clock (tis) must be met. also, a nop or deselect command must be regist ered (with tis set up time to clock) before cke goes active. once the cke is registered ?high? afte r reset, cke needs to be continuously registered ?high? until the initialization se quence is finished, including ex piration of tdllk and tzqinit. 4. the ddr3 sdram keeps its on -die termination in high-impedance state as long as reset is asserted. further, the sdram keeps its on-die termin ation in high impedan ce state after reset deassertion until cke is registered high. the odt input signal may be in undefined state until tis before cke is regis- tered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be static ally held low. in all cases, the odt input signal remains static until the pow er up initialization sequen ce is finished, including the expiration of tdllk and tzqinit.
rev. 1.1 /jan. 2011 37 5. after cke is being registered hi gh, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. (txpr = max (txs; 5 x tck) 6. issue mrs command to load mr2 wit h all application settings. (to issue mrs command for mr2, provide ?low? to ba0 and ba2, ?high? to ba1.) 7. issue mrs command to load mr3 wit h all application settings. (to issue mrs command for mr3, provide ?low? to ba2, ?high? to ba0 and ba1.) 8. issue mrs command to load mr1 with all applicati on settings and dll enabled. (to issue ?dll enable? command, provide ?low? to a0, ?high? to ba0 and ?low? to ba1-ba2). 9. issue mrs command to load mr0 with all applicati on settings and ?dll reset? (to issue dll reset com- mand, provide ?high? to a8 and ?low? to ba0-2). 10. issue zqcl command to starting zq calibration. 11. wait for both tdll k and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. figure 4. reset and initialization sequence at power-on ramping ta ck# ck tb tc td te tf tg th ti tj tk mrs 1) valid 1) mrs mrs zqcl mrs tcksrx notes: 1. from time point td until tk nop or des commands must be applied between mrs and zqcl commands. time break don t care cke ba mr3 valid mr1 mr0 mr2 valid t=500 ? t=200 ? tmin 10ns tis txpr tmrd tmrd tmrd tmod tzqinit tdllk tis tis tis static low in case rtt_nom is enabled at time tg, otherwise static high or low odt rtt valid vdd, vddq command reset #
rev. 1.1 /jan. 2011 38 1.3.2 reset initialization with stable power the following sequence is required for reset at no power interrup tion initialization. 1. asserted reset below 0.2* vdd anytime when reset is needed (all other input s may be undefined). reset needs to be main tained for minimum 100 ns. cke is pulled ?low? before reset being de- asserted (min. time 10 ns). 2. follow power-up initializati on sequence steps 2 to 11. 3. the reset sequence is now completed; ddr3 sdram is ready for normal operation. figure 5. reset procedure at power stable condition ta ck# ck command tb tc td te tf tg th ti tj tk mrs 1) valid 1) mrs mrs zqcl mrs tcksrx notes: 1. from time point td until tk nop or des commands must be applied between mrs and zqcl commands. time break don t care cke ba mr3 valid mr1 mr0 mr2 valid t=500 ? t=100 ? tmin=10ns tis txpr tmrd tmrd tmrd tmod tzqinit tdllk tis tis tis static low in case rtt_nom is enabled at time tg, otherwise static high or low vdd,vddq reset# odt rtt valid
rev. 1.1 /jan. 2011 39 1.4 register definition 1.4.1 programming the mode registers for application flexibility, various fu nctions, features and modes are pr ogrammable in four mode registers, provided by the ddr3 sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, contents of mode registers must be fully initia lized and/or re-initialized, i.e. written, after power-up and/or reset for proper oper- ation. also the contents of the mode registers can be altered by re-executing the mrs command during nor- mal operation. when programming the mode registers, even if the user chooses to modify only a sub-set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs com- mand is issued. mrs command and dll reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. the mode register set command cycle time, tmrd is re quired to complete the write operation to the mode register and is the minimum time required between two mrs commands shown in figure 6. figure 6. tmrd timing the mrs command to non-mrs command delay, tmod, is required for the dram to update the features, except dll reset, add is the minimum time required from an mrs command to a non-mrs command exclud- ing nop and des shown in figure 7. address t0 ck# ck t1 t2 ta0 ta1 tb0 tb1 tb2 tc0 tc1 tc2 mrs valid mrs valid old settings time break don t care cmd cke valid valid valid nop /des nop /des nop /des nop /des valid valid valid valid valid valid valid valid valid valid valid updating settings new settings valid valid valid valid valid valid valid valid valid valid valid valid valid valid tmrd tmod rtt_nom disenabled prior and/or after mrs command rtt_nom enabled prior and/or after mrs command odtloff+1 settings odt odt
rev. 1.1 /jan. 2011 40 figure 7. tmod timing the mode register contents can be changed using th e same command and timing requirements during nor- mal operation as long as the dram is in idle state, i.e. all banks are in the precharged state with trp satis- fied, all data bursts are completed and cke is high prior to writing into the mode register. if the rtt_nom feature is enabled in the mode register prior and/or after an mrs command, the odt signal must continu- ously be registered low ensuring rtt is in an off stated prior to the mrs command. the odt signal may be registered high after tmod has expired. if the r tt_nom feature is disabled in the mode register prior and after an mrs command, the odt signal can be regist ered either low or high before, during and after the mrs command. the mode registers are divided into various fields depending on the functionality and/or modes. t0 ck# ck address t1 t2 ta0 ta1 ta2 ta3 ta4 tb0 tb1 tb2 mrs valid valid old settings time break don t care cmd cke seetings odt valid valid nop /des nop /des nop /des nop /des valid updating settings new settings valid valid valid valid valid valid valid valid valid valid valid valid valid valid odt tmod nop /des valid valid valid valid valid valid valid valid valid valid valid odtloff+1 rtt_nom disenabled prior and/or after mrs command rtt_nom enabled prior and/or after mrs command
rev. 1.1 /jan. 2011 41 1.4.2 mode register mr0 the mode register mr0 stores the data for co ntrolling various operating mode s of ddr3 sdram. it controls burst length, read burst type, cas latency, test mo de, dll reset, wr and dll control for precharge power- down, which include various vendor specific options to make ddr3 sdra m useful for vari ous applications. the mode register is written by asserting low on cs , ras , cas , we , ba0, ba1, and ba2, while controlling the states of address pins according to figure 8. address field a6 a5 a4 a2 cas latency 0000 reserved 0010 5 0100 6 0110 7 1000 8 1010 9 1100 10 1110 11 0001 12 0011 13 0101 14 a7 mode 0normal 1test a3 read burst type 0 sequential 1 interleave a8 dll reset 0no 1yes mode register 0 ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 tm cas latency rbt dll 0* 1 wr write recovery for autoprecharge a11 a10 a9 wr (cycles) 000 16 *2 001 5 *2 010 6 *2 011 7 *2 100 8 *2 101 10 *2 110 12 *2 111 14 *2 a 15 ~ a 13 0 cl a2 a1 bl 0 1 8 (fixed) 0 1 bc4 of 8(on the fly) 1 0 bc4 (fixed) 11 reserved *1: ba2 and a13~a15 are rfu and must be programmed to 0 during mrs. *2: wr (write recovery for autoprecharge) min in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer: wrmin [cycles] = roundup (twr [ns]/tck [ns]). the wr val ue in the mode register must be programmed to be equal or larg er than wrmin. the programmed wr value is used with trp to determine tdal. *3: the table only shows the encodings for a given cas latency. for actual supported cas latenc y, please refer to speedbin tabl es for each frequency. *4: the table only shows the encodings for write recovery. for ac tual write recovery timing, please refer to ac timingtable. ba 2 0* 1 ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 a 12 ppd a12 dll control for precharge pd 0 slow exit (dll off) 1 fast exit (dll on) figure 8. ddr3 sdram mode register set (mr0) bl a1 a0 bl 0 1 8 (fixed) 0 1 bc4 of 8(on the fly) 1 0 bc4 (fixed) 11 reserved
rev. 1.1 /jan. 2011 42 1.4.2.1 burst length, type and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in figure 8. the ordering of accesses within a burst is determined by the burst length, burst type, and the start- ing column address as shown in table 12. the burst length is defined by bits a0-a1. burst length options include fixed bc4, fixed bl8, and ?on the fly? which allows bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/bc . table 12. burst type and burst order burst length read/ write starting column address (a2,a1,a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 notes 4 chop read 0 0 0 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 1,2,3 0 0 1 1,2,3,0,t,t,t,t 1,0,3,2,t,t,t,t 1,2,3 0 1 0 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 1,2,3 0 1 1 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 1,2,3 1 0 0 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 1,2,3 1 0 1 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 1,2,3 1 1 0 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 1,2,3 1 1 1 7,4,5,6,t,t,t,t 7,6,5,4,t,t,t,t 1,2,3 write 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1,2,4,5 1,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 1,2,4,5 8 read 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 2 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 2 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 2 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 2 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2, 4 notes: 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being sele cted on-the-fly via a12/bc#, the internal write opera- tion starts at the same point in time like a burst of 8 write operation. this means that during on-the-fly control, the starting point for twr and twtr will not be pulled in by two clocks. 2. 0...7 bit number is value of ca[2:0] that caus es this bit to be the first read during a burst. 3. t: output driver for data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. x: don?t care.
rev. 1.1 /jan. 2011 43 1.4.2.2 cas latency the cas latency is defi ned by mr0 (bits a9-a11) as sh own in figure 8. cas latency is the delay, is clock cycles, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half clock latencies. the overall read latency (rl) is defi ned as additive latency (al) + cas latency (cl); rl = al + cl. for more information on the supported cl and al sett ings based on the operating clock frequency, refer to ?stan- dard speed bins? on each datasheet. for detailed read operation refer to ?$paratext>? on page 74. 1.4.2.3 test mode the normal operating mode is selected by mr0 (bit a7 = 0) and a ll other bits set to the desired values shown in figure 8. programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is specified if a7 = 1. 1.4.2.4 dll reset the dll reset bit is self-clearing, mean ing that it returns back to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time that the dll reset function is used, tdllk must be met before any func tions that require the dll can be used (i.e. read commands or odt synchro- nous operations). 1.4.2.5 write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge f eature along with trp to deter- mine tdal. wr (write recovery fo r auto-precharge) min in clock cycles is calculated by dividi ng twr (in ns) by tck (in ns) and rounding up to the next integer: wrmin [cycles] = roundup (twr [ns]/tck [ns]). the wr must be programmed to be equal to or larger than twr (min). 1.4.2.6 precharge pd dll mr0 (bit a12) is used to select the dll usage during prec harge power-down mode. when mr0 (a12 = 0), or ?slow-exit?, the dll is frozen after entering prechar ge power-down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or ?f ast-exit?, the dll is mainta ined after entering precharge power-down and upon exiting power-down requires txp to be met prior to the next valid command.
rev. 1.1 /jan. 2011 44 address field tdqs mode register 1 dll 0* 1 d.i.c ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 0 dll enable 0 enable 1 disable al a7 write leveling enable 0 disabled 1 enabled 1 0* 1 rtt_nom note: rzq= 240 ? a5 a1 output driver impedance control 00 rzq/6 01 rzq/7 10 rzq/tbd 11 rzq/tbd a 4 a 3 additive latency 0 0 0 (al disabled) 01 cl-1 10 cl-2 11 reserved *1: ba2 and a8, a10, and a13~a15 are rfu and must be programmed to 0 during mrs. ba 1 0 a9 a6 a2 rtt_nom *3 0 0 0 rtt_nom disabled 001 rzq/4 010 rzq/2 011 rzq/6 100 rzq/12 *4 101 rzq/8 *4 1 1 0 reserved 1 1 1 reserved a11 tdqs enable 0 disabled 1 enabled ba 2 0* 1 1.4.3 mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on cs , ras , cas , we , high on ba0 and low on ba1 and ba 2, while controlling the states of address pins according to figure 9. qoff a 12 *2: outputs disabled - dqs, dqss, dqs s. a 12 qoff *2 0 output buffer enabled 1 output buffer disabled *2 figure 9. mr1 definition d.i.c rtt_nom level 0* 1 rtt_nom note: rzq = 240 ? *3: in write leveling mode (mr1[bit7]=1) with mr1[bit12]=1, all rtt_nom settings are allowed; in write leveling mode (mr1[bit7]=1) with mr1[bit12]=0, only rtt_nom settings of rzq/2, rzq4 and rzq/6 are allowed. *4: if rtt_nom is used during writes, only the val- ues rzq/2,rzq/4 and rzq/6 are allowed. ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3
rev. 1.1 /jan. 2011 45 1.4.3.1 dll enable/disable mr1 (a0=0), the dll is automatically di sabled when entering sefl-refresh operat ion and is automatically re-enabled upon eixt of self-refresh oper ation. any time the dll is en abled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to oc cur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be regist ered high. ddr3 sdram does not require dll for any write operation, except when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed infor- mation on dll disable operation refer to ?$paratext>? on page 55. the direct odt feature is not supported during dll-off mode. the on-die termination resistors must be disabled by con- tinuously registering in the odt pin low and/or by programmi ng the rtt_nom bits mr1 {a9,a6,a2} to {0,0,0} via a mode register set command during dll-off mode. the dynamic odt feature is not support ed at dll-off mode. user must use mr s command to set rtt_wr, mr2 {a10,a9} = {0,0}, to disable dynamic odt externally. 1.4.3.2 output driver impedance control the output driver impedance of the ddr3 sdram device is selected by mr1 (bits a1 and a5) as shown in figure 9. 1.4.3.3 odt rtt values ddr3 sdram is capable of providing two different terminati on values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1. a separate value (rtt_wr) may be programmed in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is dis- abled. 1.4.3.4 additive latency (al) additive latency (al) operation is supported to make co mmand and data bus efficient for sustainable bandwidths in ddr3 sdram. in this operation, the ddr3 sdram allows a read or write command (either with or without auto-pre- charge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (r l) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in table 13. 1.4.3.5 write leveling for better signal integrity, ddr3 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. the fly-by topology has benefits of reducing the number of st ubs and their length, but it also causes flight time skew between clock and strobe at every dram on the dimm. this makes it difficult for the co ntroller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdram suppo rts a ?write leveling? feature to allow the controller to compensate for skew. see ?$paratext>? on page 60 for more details. table 13. additive latency (al) settings note : al has a value of cl - 1 or cl - 2 as per the cl values programmed in the mr0 register a4 a3 al 0 1 0 (al disabled) 01 cl - 1 10 cl - 2 11reserved
rev. 1.1 /jan. 2011 46 1.4.3.6 output disable the ddr3 sdram outputs may be enabled/disabled by mr1 (bit a12) as shown in figure 9. when this feature is enabled (a12=1), all output pins (dqs, dqs, dqs , etc.) are disconnected from the dev ice, thus removing any loading of the output drivers. this feat ure may be useful when measuring module power , for example. for normal operation, a12 should be set to ?0?.
rev. 1.1 /jan. 2011 47 1.4.4 mode register mr2 the mode register mr2 stor es the data for controllin g refresh related features , rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on cs , ras , cas , we , high on ba1 and low on ba0 and ba2, while contro lling the states of address pins according to the table below. mr2 programming: *1: ba2, a5, a8, a11~a15 are rfu and must be programmed to 0 during mrs. *2: the rtt_wr value can be applied during writes even when rtt_no m is disabled. during write leve ling, dynamic odt is not avai lable. address field mode register 2 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 ba 1 1 ba 2 0* 1 a 12 rtt_wr 0* 1 pasr cwl srt asr ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 a2 a1 a0 partial array self refresh 000 full array 0 0 1 half array (ba[2:0]=000,001,010&011) 0 1 0 quarter array (ba[2:0]=000&001) 0 1 1 1/8th array (ba[2:0]=000) 1 0 0 3/4 array (ba[2:0]=010,011,100,101,110&111) 1 0 1 half array (ba[2:0]=100,101,110&111) 1 1 0 quarter array (ba[2:0]=110&111) 1 1 1 1/8th array (ba[2:0]=111) a10 a9 rtt_wr * 2 00 dynamic odt off (write does not affect rtt value) 0 1 rzq/4 1 0 rzq/2 11 reserved a6 auto-self-refresh (asr) 0 manual sr reference (srt) 1 asr enable figure 10. mr2 definition a7 self-refresh temperature (srt) range 0 normal operating temperature range 1 extended (optional) operating temperature range a5 a4 a3 cas write latency (cwl) 000 5 (tck (avg) 2.5ns) 001 6 (2.5ns>tck(avg 1.875ns) 010 7 (1.875ns tck (avg) 1.5ns) 011 8 (1.5ns tck (avg) 1.25ns) 100 9 (1.25ns tck (avg) 1.0ns) 101 10 (1.0ns tck (avg) 0.935ns)
rev. 1.1 /jan. 2011 48 1.4.4.1 partial array self-refresh (pasr) for hynix ddr3 sdram if pasr (partial ar ray self-refresh) is enabl ed, data located in area s of the array beyond the specified address range shown in figure 10 will be lost if self -refresh is entered. data integr ity will be maintained if trefi conditions are met and no self-refresh command is issued. 1.4.4.2 cas write latency (cwl) the cas write latency is defined by mr2 (bits a3-a5), as show n in figure 10. cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3 sdram does not sup- port any half-clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl = al + cwl. for more information on the suppor ted cwl and al settings based on the operating clock fre- quency, refer to ?standard speed bin? on each datasheet. for detailed write operationrefer to ?$paratext>? on page 85. 1.4.4.3 auto self-refresh (asr) and self-refresh temperature (srt) for more details refer to ?$paratext>? on page 64. hynix ddr3 sdrams support self-refresh operation at all supported temperatures. applications requiring se lf-refresh operation in the extended te mperature range must use the optional asr function or program the srt bit appropriately. 1.4.4.4 dynamic odt (rtt_wr) ddr3 sdram introduces a new feature ?dynamic odt?. in certai n application cases and to further enhance signal integ- rity on the data bus, it is desirable that the terminati on strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to ?$paratext>? on page 112.
rev. 1.1 /jan. 2011 49 1.4.5 mode register mr3 the mode register mr3 controls mult i purpose registers. the mode regist er 3 is written by asserting low on cs , ras , cas , we , high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the table below. mr3 programming: *1: ba2, a3-a15 are rfu and must be programmed to 0 during mrs. *2: the predefined pattern will be used for read synchronization. *3: when mpr control is set for normal operation (mr3 a[2]=0) then mr3 a[1:0] will be ignored. 1.4.5.1 multi-purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. wh en the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs co mmand is issued with the mpr disabled(mr3 bit a2=0). power-down mode, self-refresh, and any other non-rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. for det ailed mpr operatio n refer to ?$parat ext>? on page 66. 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 ba 1 1 ba 2 0* 1 a 12 address field mode register 3 mpr loc mpr figure 11. mr3 definition ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 mpr operation a2 mpr * 2 0 normal operation* 3 1 dataflow from mpr mpr address a1 a0 mpr location 00 predefined pattern* 2 01 rfu 10 rfu 11 rfu
rev. 1.1 /jan. 2011 50 2. ddr3 sdram command description and operation 2.1 command truth table (a) note 1,2,3,4 apply to the entire command truth table (b) note 5 applies to all read/write commands [ba = bank address, ra = row a ddress, ca = column address, bc = burst chop, x = don?t care, v = valid] table 14. command truth table function abbrevia- tion cke cs ras cas we ba0- ba2 a113- a15 a12- bc a10- ap a10- a9, a11 notes previous cycle current cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h hxxxxxxxx 7,8,9, 12 lhhhvvvvv single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write(bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write(bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto pre- charge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca 1. all ddr3 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. the msb of ba, ra and ca are device dens ity and configuration dependant. 2. reset is low enable command which will be used only for asynchr onous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? means either ?defined or undefined (like floating) logic level?. 5. burst reads or writes cannot be terminated or inte rrupted and fixed/on-the-fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref (both vrefdq and vrefca) must be maintained during se lf refresh operation. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refres h operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first wr ite leveling activity may not occur earlier than 512 nck after exit from self refresh. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3 sdram from registering any unwanted commands between operations. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition.
rev. 1.1 /jan. 2011 51 write with auto pre- charge (bc 4, on the fly) wras4 h h l h l l ba rfu l h ca write with auto pre- charge (bl 8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8orbc4) rd h h l h l h ba rfu v l ca read(bc4, on the fly) rds4 h h l h l h ba rfu l l ca read(bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto pre- charge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto pre- charge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto pre- charge (bl4, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l lhhhvvvvv 6,12 hxxxxxxxx power down exit pdx l h lhhhvvvvv 6,12 hxxxxxxxx zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x function abbrevia- tion cke cs ras cas we ba0- ba2 a113- a15 a12- bc a10- ap a10- a9, a11 notes previous cycle current cycle 1. all ddr3 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. the msb of ba, ra and ca are device dens ity and configuration dependant. 2. reset is low enable command which will be used only for asynchr onous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? means either ?defined or undefined (like floating) logic level?. 5. burst reads or writes cannot be terminated or inte rrupted and fixed/on-the-fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref (both vrefdq and vrefca) must be maintained during se lf refresh operation. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refres h operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first wr ite leveling activity may not occur earlier than 512 nck after exit from self refresh. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3 sdram from registering any unwanted commands between operations. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition.
rev. 1.1 /jan. 2011 52 2.2 cke truth table a) notes 1-7 apply to the entire cke truth table. b) for power-down entry and exit parameters see ?$paratext>? on page 98. c) cke low is allowed only if tmrd and tmod are satisfied. table 15. cke truth table current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down l l x maintain power-down 14,15 l h deselect or nop power-down exit 11,14 self-refresh l l x maintain self-refresh 15,16 l h deselect or nop self-refresh exit 8,12,16 bank(s) active h l deselect or no p active power-down entry 11,13,14 reading h l deselect or nop power-down entry 11,13,14,17 writing h l deselect or nop p ower-down entry 11,13,14,17 precharging h l deselect or no p power-down entry 11,13,14,17 refreshing h l deselect or nop p recharge power-down entry 11 1. cke(n) is the logic state of cke at clock edge n; c ke(n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of the ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and ac tion (n) is a result of command (n), odt is not included here. 4. all states and sequences not shown are illegal or reserved unle ss explicitly described else where in this document. 5. the state of odt does not affect the states described in this table. the odt function is no t available during self-refresh. 6. cke must be registered with the same value on tckemin consec utive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the tckemin clocks of registeration. thus, after any cke transition, cke may not tran sition from its valid level during the time period of tis + tckemin + tih. 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after deselect only after txsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh can not be entered during read or write operations . for a detailed list of restrictions see ?$paratext>? on pag e96 and see ?$paratext>? on page 98. 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care? (including float ing around vref) in self-refresh and power-down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self-refresh operaion.vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self-refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first wr ite leveling activity may not occur earlier than 512 nck after exit from self-refresh. 17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power-down is entered, oth er- wise active power-down is entered. 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, an d all timings from previous operations are satisfied (tm rd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc. ) as well as all self-refresh exit and power-down exit parameters are sa tisfied (txs, txp, txpdll, etc).
rev. 1.1 /jan. 2011 53 all banks idle h l deselect or nop precharge power-down entry 11,13,14,18 h l refresh self-refresh 9,13,18 for more details with all signals see ?$paratext>? on page 50. 10 current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) 1. cke(n) is the logic state of cke at clock edge n; c ke(n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of the ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and ac tion (n) is a result of command (n), odt is not included here. 4. all states and sequences not shown are illegal or reserved unle ss explicitly described else where in this document. 5. the state of odt does not affect the states described in this table. the odt function is no t available during self-refresh. 6. cke must be registered with the same value on tckemin consec utive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the tckemin clocks of registeration. thus, after any cke transition, cke may not tran sition from its valid level during the time period of tis + tckemin + tih. 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after deselect only after txsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh can not be entered during read or write operations . for a detailed list of restrictions see ?$paratext>? on pag e96 and see ?$paratext>? on page 98. 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care? (including float ing around vref) in self-refresh and power-down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self-refresh operaion.vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self-refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first wr ite leveling activity may not occur earlier than 512 nck after exit from self-refresh. 17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power-down is entered, oth er- wise active power-down is entered. 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, an d all timings from previous operations are satisfied (tm rd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc. ) as well as all self-refresh exit and power-down exit parameters are sa tisfied (txs, txp, txpdll, etc).
rev. 1.1 /jan. 2011 54 2.3 no operation (nop) command the no operation (nop) command is used to instru ct the selected ddr3 sdram to perform a nop (cs low and ras , cas , and we high). this prevents unwanted comman ds from being registered during idle or wait states. operations already in progress are not affected. 2.4 deselect command the deselect function (cs high) prevents new commands from being executed by the ddr3 sdram. the ddr3 sdram is effectively deselected. oper ations already in progress are not affected.
rev. 1.1 /jan. 2011 55 2.5 dll-off mode ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; this will disable the dll for subseq uent opera- tions until a0 bit is set back to ?0?. the mr1 a0 bit fo r dll control can be switched either during initialization or later. refer to ?$paratext>? on page 58. the dll-off mode operations listed below are an op tional feature for ddr3. the maximum clock frequency for dll-off mode is specified by the parameter tckd ll_off. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll-off mode is only required to support setting of both cl=6 and cwl=6. dll-off mode will affect the read data clock to data strobe relationship (tdqsck), but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to controller time domain. comparing with dll-on mode, where tdqsck starts fr om the rising clock edge (al+cl) cycles after the read command, the dll-off mode tdqsck starts (al+ cl-1) cycles after the read command. another differ- ence is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is signif icantly larger than in dll-on mode. the timing relations on dll-off mode read operatio n are shown at following timing diagram (cl=6, bl=8): figure 12. dll_off mode read timing operation note: the tdqsck is used fere for dqs,dqs# and dq to have a simplified diagram; the dll_off shift will affect both timings in the same way and the skew between all dq and dqs,dqs# signals sill still be tdqsq. ck # ck command address dqs, dqs# (dll_on) nop nop nop nop nop nop nop nop nop dq (dll_on) din b transitioning data don t care read nop bank. col b din b+2 din b+3 rl(dll_on)=al+cl=6(cl=6,al=0) din b+4 din b+6 din b+7 din b din b+2 din b+3 din b+4 din b+6 din b+7 din b din b+2 din b+3 din b+4 din b+6 din b+7 cl=6 rl(dll_off)=al+(cl-1)=5 tdqsck(dll_off)_min tdqsck(dll_off)_max dqs, dqs# (dll_off) dqs, dqs# (dll_off) dq (dll_off) dq (dll_off) din b+2 din b+5 din b+2 din b+5 din b+2 din b+5
rev. 1.1 /jan. 2011 56 2.6 dll on/off switching procedure ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; this will disable the dll for subseq uent opera- tions until a0 bit is set back to ?0?. 2.6.1 dll ?on? to dll ?off? procedure to switch from dll ?on? to dll ?off? requires the frequency to be changed during self-refresh, as outlined in the following procedure: 1. starting from idle state (all banks pre-charged, all timings fulfilled, and drams on-die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll). 2. set mr1 bit a0 to ?1? to disable the dll. 3. wait tmod. 4. enter self refresh mode; wait until (tcksre) is satisfied. 5. change frequency, in guidance with '2.7 input clock frequency change' on page 58. 6. wait until a stable clock is availabl e for at least (tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt f eatures were enabled in the mode registers when self refresh mode was enter ed, the odt signal must continuously be reg- istered low until all tmod timings from any mrs co mmand are satisfied. if both odt features were disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8. wait txs, then set mode registers with appropria te values (especially an update of cl, cwl and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, then dram is ready for next command. figure 1. figure 13. dll switch sequence from dll-on to dll-off t0 ck# ck t1 ta0 ta1 tb0 tc0 td0 td1 te0 te1 tf0 nop sre(3) nop valid(8) srx(6) nop mrs(7) mrs(2) odt tmod notes: 1. starting with idle state, rtt in hi-z state 2. disable dll by setting mr1 bit a0 to 1 3. enter sr 4. change frequency 5. clock must be stable tcksrx 6. exit sr 7. update mode registers with dll off parameters setting 8. any valid command time break don t care cmd odt: static low in case rtt_wr is enabled, otherwise static low or high valid(8) valid(8) tcksre tcksrx(5) txs tmod (4) tckesr cke (1) nop
rev. 1.1 /jan. 2011 57 2.6.2 dll ?off? to dll ?on? procedure to switch from dll ?off? to dll ?on? (with required the frequency change) during self-refresh: 1. starting from idle state (all banks pre-charged, all timings fulfilled, and drams on-die termination resistors (rtt) must be in high impedance state before self-refresh mode is entered.) 2. enter self refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with '2.7 input clock frequency change' on page 58. 4. wait until a stable clock is availabl e for at least (tcksrx) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be re gistered high until tdllk timing from subsequent dll reset command is sati sfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continu- ously be registered low until tdllk timings from subsequent dll reset co mmand is satisfied. if both odt features are disabled in the mode regi sters when self refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to ?0? to enable the dll. 7. wait tmrd, then set mr1 bit a8 to ?1? to st art dll reset. 8. wait tmrd, then set mode registers with appropri ate values (especially an update of cl, cwl and wr may be necessary. after tmod satisfied from any proceeding mrs command, may also be issued during or after tdllk.) 9. wait for tmod, then dram is ready for next co mmand (remember to wait tdllk after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued. figure 14. dll switch sequence from dll off to dll on t0 ck# ck ta0 ta1 tb0 tc0 tc1 td0 te0 tf1 tg0 th0 sre(2) nop valid(9) srx(5) mrs(6) mrs(7) nop odt tmod notes: 1. starting with idle state 2. enter sr 3. change frequency 4. clock must be stable tcksrx 5. exit sr 6. set dll on by mr1 a0=0 7. update mode registers 8. any valid command time break don t care cmd odt: static low in case rtt_wr is enabled, otherwise static low or high valid (3) txs tmrd tmrd tcksrx(4) tckesr cke (1) mrs(8) odtloff+ 1xtck tdllk
rev. 1.1 /jan. 2011 58 2.7 input clock frequency change once the ddr3 sdram is initialized, the ddr3 sdram re quires the clock to be ?stable? during almost all states of normal operation. this means once the clock frequency has been set and is to be in the ?stable state?, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specifications. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mod and (2) precha rge power-down mode. outside of these two modes, it is ille- gal to change the clock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self-refresh mode and t cksre has been satisfied, the state of the clock becom es a don?t care. once a don?t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to t cksrx. when entering and exiting self-refresh mode for the sole purpose of changing the clock frequency, the self-refresh entry and exit specifications mu st still be met as outlined in see ?$ paratext>? on page 96. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency spec- ified for the particular speed grade. any frequency change below the minimum operating frequency would require the use of dll_on-mode->dll_off-mode transition sequence, refer to ?$paratext>? on page 56. the second condition is when the ddr3 sdram is in pr echarge power-down mode (either fast exit mode or slow exit mode). if the r tt_nom feature was enabled in the mode regi ster prior to entering precharge power down mode, the odt signal must continuously be regi stered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in th e mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case. a minimum of t ck- sre must occur after cke goes low before the cl ock frequency may change. the ddr3 sdram input clock frequency is allowed to change only within th e minimum and maximum oper ating frequency specified for the particular speed grade. during the input clock fr equency change, odt and cke must be held at stable low levels. once the input clock frequency is change d, stable new clocks must be provided to the dram t cksrx before precharge power-down may be exited; af ter precharge power-down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs com- mands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. during dll re-lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequ ency. this process is depicted in figure 15 on page 59.
rev. 1.1 /jan. 2011 59 t0 t1 tc0 t2 ta0 tb0 tc1 td0 td1 te0 te1 previous clock frequency new clock fequency tch tcl tck tcksre tchb tclb tckb tcksrx tcke tis tih tis tih nop nop nop nop nop mrs nop valo dll reset vaud tih tis taofpd/taof txp high-z high-z ck# ck cke addr odt dq dm enter precharge power-down mode frequency change exit precharge power-down mode tdllk indlcates a break in time scale don t care note 1: applicable for both slow exit and fast exit precharge power-down note 2: taofpd and taof must be statisfied and outputs high-z prior to t1; refer to odt timing section for exact requirements note 3: if the rtt_nom feature was enabled in the mode register prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off st ate, as shown in figure 6. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high is this case. tcpded cmd dqs, dqs# figure 15. change frequency during precharge power-down
rev. 1.1 /jan. 2011 60 2.8 write leveling for better signal integrity, the ddr3 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. the fly-by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every dram on th e dimm. this makes it diffi- cult for the controller to maintain tdqss, tdss, and tdsh specificat ion. therefore, the ddr3 sdram sup- ports a ?write leveling? feature to allo w the controller to compensate for skew. the memory controller can use the ?write leveling? feature and feedback from the ddr3 sdram to adjust the dqs-dqs to ck-ck relationship. the memory cont roller involved in the leveling must have adjustable delay setting on dqs-dqs to align the rising edge of dqs-dqs with that of the clock at the dram pin. the dram asynchronously feeds back ck-ck , sampled with the rising edge of dqs-dqs , through the dq bus. the controller repeatedly delays dqs-dqs until a transition from 0 to 1 is detected. the dqs-dqs delay estab- lished though this exercise would ensure tdqss specification. besides tdqss, tdss and tdsh specification also needs to be fulfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs-dqs signals. depending on the actual tdqss in the application, the actual values for tdqsl and tdqs h may have to be better than the absolute limits provided in the chapter ?ac timing parameters? in order to satisfy tdss and td sh specification. a concept ual timing of this scheme is shown in figure 16. figure 16. write leveling concept dqs-dqs driven by the controller during leveling mode must be terminated by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. one or more data bits should carry the leveling feedb ack to the controller across the dram configurations x4,x8 and x16. on a x16 device, both byte lanes sh ould be leveled independentl y. therefore, a separate feedback mechanism should be available for each byte lane. the upper data bits should provide the feedback of the upper diff_dqs (diff_udqs) to clock relationship whereas the lower data bits would indicate the lower diff_dqs (diff_ldqs) to clock relationship. 2.8.1 dram setting for writ e leveling & dram terminat ion function in that mode dram enters into write leveling mode if a7 in mr1 set ?high? and after fi nishing leveling, dram exits from write leveling mode if a7 in mr1 set ?low? (table 16) . note that in write le veling mode, only dqs/dqs termi- nations are activated and deact ivated via odt pin, unlike normal operation (table 17). t0 ck# ck dq t1 t2 t3 t4 t5 t6 t7 diff_dqs push dqs to capture 0-1 transiton tn t0 t1 t2 t3 t4 t5 t6 0 or 1 0 0 0 0 or 1 1 1 1 source ck# ck diff_dqs destination dq diff_dqs
rev. 1.1 /jan. 2011 61 2.8.2 procedure description memory controller initiates lev eling mode of all drams by setting bit 7 of mr1 to 1. with entering write level- ing mode, the dq pins are in unde rfined driving mode. du ring white leveling mode , only nop or deselect commands are allowed, as well as an mrs command to change qoff bit (mr1[a12]) and an mrs command to exit (mr1[a7]). upon exiting wr ite leveling mode, the mrs command pe rforming the exit (mr7[a7]=0) may also change mr1 bits of a12-a11, a9, a6-a5, and a2-a1. since the controller levels one rank at a time, the output of other ranks must be disabl ed by setting mr1 bit a12 to 1. c ontroller may assert odt after tmod, time at which time the dram is ready to accept the odt signal. the controller may drive dqs low and dqs high after a delay of twldqsen, at which time dram has applied on-die termination on these signals. after tdqsl and twlmrd, controller provides a single dqs, dqs edge which is used by the dram to sample ck-ck driven from controller. twlmrd (max) timing is con- troller dependent. dram samples ck-ck status with rising edge of dqs-dqs and provides feedback on all the dq bits asyn- chronously after twlo timing. either one or all data bits (?prime dq bit(s)?) provide the leveling feedback. the dram?s remaining dq bit are driven low statically after the first sampling procedure. there is a dq output uncertainty of twloe defined to allow mismatch on dq bi ts. the twloe period is defined from the transition of the earliest dq bit to the corresponding transiti on of the latest dq bit. there are no read strobes (dqs/dqs ) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs-dqs delay setting and launches the next dqs/dqs pulse after some time, which is controller depen- dent. once a 0 to 1 transition is detected, the contro ller locks dqs-dqs delay setting and write leveling is achieved for the device. figure 17 describes the timing diagram and parameters for the overall write leveling procedure. table 16. mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 table 17. dram termination function in the leveling mode note : in write leveling mode with its output buffer disabled (mr1[bit7]=1 with mr1[bit12]=1) all rtt_nom set- tings are allowed; in write leveling mode with its out put buffer enabled (mr1[bit7]=1 with mr1[bit12]=0) only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. odt pin @dram dqs/dqs termination dqs termination de-asserted off off asserted on off
rev. 1.1 /jan. 2011 62 figure 17. timing details of write leveling sequence [dqs-dqs is capturing ck-ck low at t1 and ck-ck high at t2 ck*5 late remaining dqs notes: 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low, as shown in above figure, and maintained at this state through out the leveling procedure. 2. mrs: load mr1 to enter write leveling mode 3. nop: nop or deselect 4. diff_dqs is the differential data strobe (dqs, dqs#). tiiming reference points are the zero crossings. dqs is shown with sol id line, dqs# is shown with dotted line 5. ck,ck#: ck is shown with solid line, where as ck# is drawn with dotted line. 6. dqs,dqs# needs to fulfill minimum pulse width requirements td qsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent. mrs nop nop nop nop nop nop nop nop nop nop nop twls twlh twls tmod twldqsen tdqsl*6 tdqsh*6 tdqsl*6 tdqsh*6 twlmrd twlo twloe twlo ck cmd odt diff_dqs*4 prime dq*1 t1 t2 twlh *3 *2 twlo twlo twloe twlo twlo twlo twloe twlmrd one prime dq: early remaining dqs all dqs are prime: late prime dqs*1 early prime dqs*1 undefined driving mode time break don t care
rev. 1.1 /jan. 2011 63 2.8.3 write leveling mode exit the following sequence describes how the write leveling mode should be exited: 1. after the last rising strobe edge (see~t0), stop driv ing the strobe signals (see ~tc0). note: from now on, dq pins are in undefined driving mode, and will remain unde fined, until tmod afte r the respective mr command(te1). 2. drive odt pin low (tis must be satisfied) and continue registering low. (see tb0). 3. after the rtt is switched off, disable write level mode via mrs command (see tc2). 4. after tmod is satisfied(te1), any valid command may be registered. (mr commands may be issued after tmrd(td1). figure 18. timing details of write leveling exit valid t0 ck# ck address t1 t2 ta0 tb0 tc0 tc1 tc2 td0 td1 te0 nop nop nop nop nop valid nop mrs nop te1 nop valid nop mr1 tmrd valid odtloff tmod tis taofmin taofmax twlo result=1 rtt_nom notes: 1. the dq result=1 between ta0 is a result of the dqs, dqs# signals captuting ck high just after the t0 state. 2. refer to figure 12 for specific twlo timing. undefined driving mode time break don t care transitioning cmd odt rtt_ dqs_dqs# dqs_dqs# rtt_dq dq *1
rev. 1.1 /jan. 2011 64 2.9 extended temperature usage hynix ddr3 sdram devices support the following options or requirements referred to in this material: a. auto self-refresh supported b. extended temperature range supported c. double refresh required for operation in the extended temperature range 2.9.1 auto self-refresh mode-asr mode ddr3 sdram provides an auto self-refresh mode (asr ) for application ease. asr mode is enabled by set- ting mr2 bit a6=1 b and mr2 bit a7=0 b . the dram will manage se lf-refresh entry in ei ther the normal or extended (optional) te mperature rang es. in this mode, the dram will al so manage self-refresh power con- sumption when the dram operating temperature changes, lower at low temperatures and higher at high tem- peratures. if the asr mode is not enabled(mr2 bit. a6=0b), the srt bit(mr2 a7) must be manually programmed with the operating temperature range required during self-refresh operation. support of the asr option does not automatically imply support of the extended temperature range. table 18. mode register description field bits description asr mr2(a6) auto self-refresh (asr) when enabled, ddr3 sdram automatically provides self-refresh power manage- ment functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate t oper during subsequent self-refresh operation 0=manual sr reference (srt) 1=asr enable srt mr2(a7) self-refresh temperature (srt) range if asr=0, the srt bit must be programmed to indicate t oper during subsequent self- refresh operation if asr=1, srt bit must be set to 0 b 0=normal operating temperature range 1=extended operating temperature range
rev. 1.1 /jan. 2011 65 2.9.2 self-refresh temperature range-srt srt applies to devices supporting extended temperatur e range only. if asr=0b, the self-refresh tempera- ture (srt) range bit must be programmed to guarantee proper self-refresh operation. if srt=0b, then the dram will set an appropriate refresh ra te for self-refresh operation in the normal temper ature rang e. if srt=1b then the dram will set an appropriate, potentially diff erent, refresh rate to allow self-refresh opera- tion in either the normal or extended temperature rang es. the value of the str bit can effect self-refresh power consumption, please refer to the idd table for details. table 19. self-refresh mode summary mr2 a[6] mr2 a[7] self-refresh operation allowed operating temperature range for self-refresh mode 00 self-refresh rate appropriate for the nor- mal temperature range normal(0-85 ) 01 self-refresh rate appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range. the value of the srt bit can effect self-refresh power consumption, please refer to the idd table for details. normal and extended(0-95 ) 10 asr enabled (for devices supporting asr and normal temperature range). self- refresh power consumption is tempera- ture dependent normal(0-85 ) 10 asr enabled (for devices supporting asr and extended temperature range). self- refresh power consumption is tempera- ture dependent normal and extended(0-95 ) 1 1 same as mr2 a[6] = 0, mr2 a[7] = 1
rev. 1.1 /jan. 2011 66 memory core (all banks precharged) multi purpose register pre-defined data for reads dq, dm, dqs, dqs# mr3[a2] 2.10 multi purpose register the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. the basic concept of the mpr is shown in figure 19. figure 19. mpr block diagram to enable the mpr, a mode register set (mrs) comma nd must be issued to mr3 register with bit a2=1, as shown in table 20. prior to issuing the mrs command, all banks must be in the id le in the idle state (all banks precharged and trp met). once the mpr is enabled, any subse quent rd or rda commands will be redirected to the multi purpose register. the resultin g operation, when a rd or rda command is issued, is defined by mr3 bits a[1:0] when the mpr is enabled as shown in table 21. when the mpr is enabled, only rd or rda commands are allo wed until a subsequent mrs command is issued with the mpr disabled(mr3 bit a2=0). note that in mpr mode rda has the same functionalit y as a read command which means the auto precharge part of rda is ignored. power-down mode, self-refresh, and any other non-rd/rda com- mand is not allowed during mpr enable mode. t he reset function is suppor ted during mpr enable mode. table 20. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr-loc 0b don?t care (0b or 1b) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see table 21 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0]
rev. 1.1 /jan. 2011 67 2.10.1 mpr functional description ? one bit wide logical interface via all dq pins during read operation. ? register read on x4: ? dq[0] drives information from mpr. ? dq[3:1] either drive the same informa tion as dq[0], or they drive 0b. ? register read on x8: ? dq[0] drives information from mpr. ? dq[7:1] either drive the same informa tion as dq[0], or they drive 0b. ? register read on x16: ? dql[0] and dqu[0] driv e information from mpr. ? dql[7:1] and dqu[7:1] either drive the same information as dql[0], or they drive 0b. ? addressing during for multi purpose register reads for all mpr agents: ? ba[2:0]: don?t care ? a[1:0]: a[1:0] must be equal to ?00?b.da ta read burst order in nibble is fixed. ? a[2]: for bl=8, a[2] must be equal to 0b, burst or der is fixed to [0,1,2,3,4 ,5,6,7],* for burst chop 4 cases, the burst order is switched on nibble base a[2]=0b, burst order: 0,1,2,3* a[2]=1b, burst order: 4,5,6,7* ? a[9:3]: don?t care ? a10/ap: don?t care ? a12/bc: selects burst chop mode on-the-fly, if enabled within mr0. ? a11,a13,...(if available): don?t care ? regular interface functionality during register reads: ? support two burst ordering which are switched with a2 and a[1:0]=00b. ? support of read burst chop (mrs and on-the-fly via a12/bc) ? all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3 sdram. ? regular read latencies and ac timings apply. ? dll must be locked prior to mpr reads. note: * burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent.
rev. 1.1 /jan. 2011 68 2.10.2 mpr register address definition table 21 provides an overview of the available data locations, how they are addr essed by mr3 a[1:0] during a mrs to mr3, and how their individual bits are mapped into the burst order bits during a multi purpose reg- ister read. 2.10.3 relevant timing parameters the following ac timing parameters are important fo r operating the multi purpose register: trp, tmrd, tmod, and tmprr. for more details refer to ?$paratext>? on page 148. 2.10.4 protocol example protocol example (this is one example): read out predetermined read-calibration pattern. description: multiple re ads from multi purpose register, in order to do system level read timing calibration based on predetermined and standardized pattern. protocol steps: ? precharge all. ? wait until trp is satisfied. ? mrs mr3, opcode ?a2=1b? and ?a[1:0]=00b? ? redirect all subsequent reads into the multi purpose register, and load pre-defined pattern into mpr. ? wait until tmrd and tmod are satisfied (multi purpos e register is then ready to be read). during the table 21. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre-defined data patt ern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre-defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6,7 pre-defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 11b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 note: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent.
rev. 1.1 /jan. 2011 69 period mr3 a2=1, no data write operation is allowed. ? read: ? a[1:0]=?00?b (data burst order is fixe d starting at nibble, always 00b here) ? a[2]=?0?b (for bl=8, burst orde r is fixed as 0,1,2,3,4,5,6,7) ? a12/bc=1 (use regular burst length of 8) ? all other address pins (including ba[2:0] and a10/ap): don?t care ? after rl=al+cl, dram bursts out the predefined read calibration pattern. ? memory controller repeats these calibration reads unt il read data capture at memory controller is opti- mized. ? after end of last mpr read burs t, wait until tmprr is satisfied. ? mrs mr3, opcode ?a2=0b? and ?a[1:0]=valid data but value are don?t care? ? all subsequent read and write accesses will be re gular reads and writes from/to the dram array. ? wait until tmrd and tmod are satisfied. ? continue with ?regular? dram commands, like activate a memory bank for regular read or write access,... ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 20. mpr readout of predefined pattern, bl8 fixed burst order, single readout t0 ta tb0 tb1 tc0 tc1 tc2 tc3 tc4 tc5 tc6 nop mrs read nop nop nop nop nop nop tc7 tc8 tc9 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmprr tmod ck# ck cmd ba a[2] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *1 *1 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. time break don t care
rev. 1.1 /jan. 2011 70 figure 21. mpr readout of predefined pattern, bl8 fixed burst order, back-to-back readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea mrs nop nop write valid 3 valid 3 0 0 2 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *1 *1 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. time break don t care valid 2 0 2 0 valid valid valid valid valid rl tccd *1 tmprr
rev. 1.1 /jan. 2011 71 figure 22. mpr readout of predefined pattern, bc4, lower nibble then upper readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *2 *3 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0...3. 4. a[2]=1 selects upper 4 nibble bits 4...7. time break don t care valid 2 0 1 valid valid valid valid valid rl tccd *1 tmprr *1 *1 *2 *4
rev. 1.1 /jan. 2011 72 figure 23. mpr readout of predefined pattern, bc4, upper nibble then lower readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 1 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *2 *3 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0...3. 4. a[2]=1 selects upper 4 nibble bits 4...7. time break don t care valid 2 0 0 valid valid valid valid valid rl tccd *1 tmprr *1 *1 *2 *4
rev. 1.1 /jan. 2011 73 2.11 active command the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0-ba2 inputs selects the bank, and the address provided on inputs a0-a15 selects the row. this row remains active (or open) for accesses unt il a precharge command is issued to that bank. a pre- charge command must be issued before opening a different row in the same bank. 2.12 precharge command the precharge command is used to dea ctivate the open row in a particul ar bank or the open row in all banks. the bank(s) will be available fo r a subsequent row activation a sp ecified time (trp) after the pre- charge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (i dle state) or if the previous ly open row is already in the process of precha rging. however, the prechar ge period will be determined by the last precharge com- mand issued to the bank.
rev. 1.1 /jan. 2011 74 2.13 read operation 2.13.1 read burst operation during a read or write command, ddr3 will suppor t bc4 and bl8 on the fly using address a12 during the read or write(auto precharge can be enabled or disabled). a12=0, bc4(bc4=burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column address. figure 24. read burst operation rl=5 (al=0,cl=5,bl8) figure 25. read burst operation rl=9 (al=4,cl=5,bl8) read bank, col n t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop mrs nop nop nop nop trpre trpst dq2 cl=5 dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 note: 1. bl8, rl=5, al=0, cl=5. 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration: other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during read command at t0. transitioning data don t care rl=al+cl read bank col n t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop trpre dq2 al=4 dout n dout n+1 dout n+2 note: 1. bl8, rl=9, al=(cl-1), cl=5. 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during read command at t0. transitioning data don t care cl=5 rl=al+cl
rev. 1.1 /jan. 2011 75 2.13.2 read timing definitions read timing is shown in figure 26 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsck min/max describes the allowed range for a rising data strobe edge relative a ck,ck#. ? tdqsck is the actual position or a rising strobe edge relative to ck,ck#. ? tqsh describes the dqs,dqs# differential output high time. ? tdqsq describes the latest valid tran sition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: ? tqsl describes the dqs,dqs# differential output low time. ? tdqsq describes the latest valid tran sition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. tdqs; both rising/falling edges of dqs, no tac defined. figure 26. read timing definition ck# ck tdqsck, min tdqsck dqs dqs tqh tdqsq ck# tdqsq tqh tqsh tqsl ck# tdqsck, max tdqsck, min tdqsck, max rising strobe region rising strobe region
rev. 1.1 /jan. 2011 76 2.13.2.1 read timing; clock to data strobe relationship clock to data strobe relationship is shown in figure 27 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck,ck#. ? tdqsck is the actual position of a rising strobe edge relative to ck,ck#. ? tqsh describes the data strobe high pulse width. falling data strobe edge parameters: ? tqsl describes the data strobe low pulse width. tlz (dqs), thz (dqs) for preamble/posta mble (see 2.13.2.3 and figure 29) figure 27. clock to data strobe relationship rl measured to this point clk/clk# tdqsck(min) tlz(dqs)min tqsh tqsl tdqsck(min) tqsh tqsl tdqsck(min) tqsh tqsl tdqsck(min) thz(dqs)min trpre dqs,dqs# early strobe trpst tlz(dqs)max bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 tdqsck(max) tdqsck(max) tdqsck(max) tdqsck(max) trpst thz(dqs)max bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 dqs,dqs# late strobe tqsh tqsl tqsh tqsl trpre note: 1. within a burst, rising strobe edge is not necessarily fixed to be always at tdqsck(min) or tdqsck(max). instead, risin g edge can vary between tdqsck(min) and tdqsck(max). 2. notwithstanding note 1, a rising strobe edge with tdqsck(max) at t(n) can not be immediately followed by a rising strobe edge with tdqsck(min) at t(n+1). this is because other timing relactionship (tqsh, tqsl) exist: if tdqsck(n+1) < 0: tdqsck(n) < 1.0 tch ? (tqshmin + tqslmin) - | tdqsck(n+1) | 2. the dqs,dqs# differential output high time is defined by tqsh and the dqs,dqs# differential output low time is def ined by tqsl. 3. likewise, tlz(dqs)min and thz(dqs)min are not tied to tdqsckmin(early strobe case) and tlz(dqs)max and thz(dqs)max are not tied to tdqsckmax(late strobe case). 4. the minimum pulse width of read preamble is defined trpre(min). 5. the maximum read postamble is bound by tdqsck(min( plus tqsh(min) on the left side and thzdsq(max) on the right si de. 6. the minimum pulse width read postamble is defined by trpst(min). 7. the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side.
rev. 1.1 /jan. 2011 77 2.13.2.2 read timing; data strobe to data relationship the data strobe to data relationship is shown in figure 28 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsq describes the latest valid tran sition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. filling data strobe edge parameters: ? tdqsq describes the latest valid tran sition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. tdqsq; both rising/falling edge s of dqs, no tac defined figure 28. data strobe to data relationship read bank col n to ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop tdqsq(max) trpst dq2(last data valid) rl = al+cl dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout n+2 dout n+4 dout n+5 dout n+6 dout n+7 trpre toh toh dout n+3 dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+6 dout n+7 dout n+5 note: 1. bl=8, rl=5 (al=0, cl=5) 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=] and a12=1 during read command at t0. 5. output timings are referenced to vddq/2, and dll on for locking. 6. tdqsq defines the skew between dqs, dqs# to data and does net define dqs, dqs# to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or la te) within a burst. transitioning data don t care all dqs collectively dq2 (first data no longer valid) tdqsq(max)
rev. 1.1 /jan. 2011 78 2.13.2.3 tlz(dqs), tlz (dq), thz(dqs), thz (dq) calculation thz and tlz transitions occur in the same time window as valid data transitions. these parameters are refer- enced to a specific voltage level that specifies when the device output is no longer driving thz(dqs) and thz (dq), or begins driving tlz(dqs), tlz (dq). figure 29 sh ows a method to calculate the point when the device is no longer driving thz(dqs) and thz (dq), or begins driving tlz(dqs), tlz (dq) by measuring the signal at two different voltages. the actual voltage measurement po ints are not critical as long as the calculation is consistent. the parameters tlz(dqs), tlz (dq), thz(dqs), and thz (dq) are defined as singled ended. figure 29. tlz and thz method for calculating transitions and endpoints ck# ck vtt + 2x mv vtt + x mv vtt - 2x mv vtt - x mv tlz(dqs): ck ? ck# rising crossing at rl - 1 tlz(dq): ck ? ck# rising crossing at rl tlz(dqs),tlz(dq) tlz(dqs),tlz(dq) begin point = 2*t1 - t2 tlz ck# ck thz(dqs),thz(dq) with bl8: ck ? ck# rising crossing at rl + 4 nck thz(dqs),thz(dq) with bl4: ck ? ck# rising crossing at rl + 2 nck thz(dqs),thz(dq) enn point = 2*t1 - t2 thz voh - x mv voh - 2x mv voh + x mv voh + 2x mv tlz(dqs),tlz(dq)
rev. 1.1 /jan. 2011 79 2.13.2.4 trpre calculation method for calculating differential pulse widths for trpre is shown in figure 30. figure 30. method for calculating trpre transitions and endpoints 2.13.2.5 trpst calculation method for calculating differential pulse widths for trpst is shown in figure 31. figure 31. method for calculating trpre transitions and endpoints ck ck vtt dqs sibgke ebded signal, provided as background information vtt dqs single ebded signal, provided as background information vtt tc td tb dqs - dqs resulting differential signal, relevant for trpre specification t1 trpre_begin t2 trpre_end 0 ta trpre ck ck vtt dqs sibgke ebded signal, provided as background information vtt dqs single ebded signal, provided as background information vtt tc td tb dqs - dqs resulting differential signal, relevant for trpst specification t1 trpst_begin t2 trpst_end 0 ta trpst td_trpst_def
rev. 1.1 /jan. 2011 80 figure 32. read(bl8) to read(bl8) figure 33. read(bc4) to read(bc4) to ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre trpst dq2 rl=5 dout n dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout n+5 dout n+6 dout n+7 dout b dout b+1 dout n+1 dout n+2 dout n+3 dout n+4 rl=5 note: 1. bl8, rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during read command at t0 and t4 to ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre trpst dq2 rl=5 dout n dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout n+5 dout n+6 dout n+7 dout b dout b+1 dout n+1 dout n+2 dout n+3 dout n+4 rl=5 note: 1. bl8, rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during read command at t0 and t4 to ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre trpst dq2 rl=5 dout n dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout n+5 dout n+6 dout n+7 dout b dout b+1 dout n+1 dout n+2 dout n+3 dout n+4 rl=5 note: 1. bl8, rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during read command at t0 and t4 t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpst dq2 rl=5 dout n dout b+2 dout b+3 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout b dout b+1 dout n+1 dout n+2 dout n+3 rl=5 note: 1. bl4, rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl4 setting activated by either mr0[a1:0=10] or mr0[a1:0=01] and a12=0 during read command at t0 and t4. trpre trpst trpre
rev. 1.1 /jan. 2011 81 figure 34. read(bl8) to write(bl8) figure 35. read(bc4) to write(bc4) otf t0 ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop trpre twpst dq2 rl=5 dout n din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop nop bank. col n bank. col b dout n+5 dout n+6 dout n+7 din b din b+1 dout n+1 dout n+2 dout n+3 dout n+4 wl=5 note: 1. bl8, rl=5 (cl=5, al=0), wl=5 (cwl=5, al=0) 2. dout n (or b) = data-out from column, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1=01] and a12=1 during read command at t0 and write command a t t6 t15 nop write read to write command delay = rl+tccd+2tck-wl tbl= 4 clocks twr twtr trpst twpre command3 dqs, dqs# to ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre twps t dq2 rl=5 dout n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop write bank. col n bank. col b din b din b+1 dout n+1 dout n+2 dout n+3 wl=5 note: 1. bc4, rl=5 (cl=5, al=0), wl=5 (cwl=5, al=0) 2. dout n = data-out from column, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during read command at t0 and write command at t4. t15 nop read to write command delay = rl+tccd/2+2tck-wl tbl= 4 clocks twr twtr trpst twpre twpst command3 dqs, dqs#
rev. 1.1 /jan. 2011 82 figure 36. read(bl8) to read(bc4) otf figure 37. read(bc4) to read(bl8) otf t0 ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre trpst dq2 rl=5 dout n dout b+2 dout b+3 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout n+5 dout n+6 dout n+7 dout b dout b+1 dout n+1 dout n+2 dout n+3 dout n+4 rl=5 note: 1. rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=01] and a12=1 during read command at t0. bc4 setting activated by either mr0[a1:0=01] and a12=0 during read command at t4. t0 ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpst dq2 rl=5 dout n dout b+2 dout b+3 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop read bank. col n bank. col b tccd dout b dout b+1 dout n+1 dout n+2 dout n+3 rl=5 note: 1. rl=5 (cl=5, al=0) 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during read command at t0. bl8 setting activated by either mr0[a1:0=01] and a12=1 during read command at t4. trpre trpst dout b+6 dout b+7 dout b+4 dout b+5
rev. 1.1 /jan. 2011 83 figure 38. read(bc4) to write(bl8) otf figure 39. read(bl8) to write(bc4) otf t0 ck# ck t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop trpre twpst dq2 rl=5 dout n din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop write bank. col n bank. col b din b din b+1 dout n+1 dout n+2 dout n+3 wl=5 note: 1. rl=5 (cl=5, al=0), wl=5 (cwl-1, al=0) 2. dout n (or b) = data-out from column, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during read command at t0. bl8 setting activated by either mr0[a1:0=01] and a12=1 during write command at t4. t15 nop read read to write command delay = rl+tccd/2+2tck-wl tbl= 4 clocks twr twtr trpst twpre a ddress4 command3 dqs, dqs# t0 ck# ck address4 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop trpre twpst dq2 rl=5 dout n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 read nop nop nop nop bank. col n bank. col b dout n+5 dout n+6 dout n+7 din b din b+1 dout n+1 dout n+2 dout n+3 dout n+4 wl=5 note: 1. rl=5 (cl=5, al=0), wl=5 (cwl=5, al=0) 2. dout n = data-out from column, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=01] and a12=1 during read command at t0. bc4 setting activated by either mr0[a1:0=01] and a12=0 during write command at t6. t15 nop write read to write command delay = rl+tccd+2tck-wl tbl= 4 clocks trpst twpre command3 dqs, dqs#
rev. 1.1 /jan. 2011 84 2.13.3 burst read operation followed by a precharge the minimum external read command to precharge command spacing to the same bank is equal to al + trtp with trtp being the internal read command to precharge command delay. note that the minimum act to pre timing, tras, must be satisfied as well. the minimum value for the internal read command to precharge command delay is given by trtp.min = max( 4 x nck, 7.5 ns). a new bank active command may be issued to the same bank if the following tow conditions are satisfied simultaneously: 1. the minimum ras precharge time (trp.min) has be en satisfied from the clock at which the precharge begins. 2. the minimum ras cycle time (trc.min) from t he previous bank activation has been satisfied. examples of read commands followed by precha rge are show in figure 40 and figure 41. figure 37. read to precharge, rl = 5, al = 0, cl = 5, trtp = 4, trp = 5 figure 40. read to precharge, rl = 5, al = 0, cl = 5, trtp = 4, trp = 5 figure 41. read to precharge, rl = 8, al = cl - 2, cl = 5, trtp = 6, trp = 5 t0 ck# ck address t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 pre nop nop act nop nop nop rl = al + cl dq do n d) n+2 do n+3 do n+4 do n+5 do n+6 do n+7 transitioning data don t care t11 t12 t13 t14 nop nop nop nop nop nop bank. col n bank a, (or all) do n do n+1 do n+1 do n+2 do n+3 note: 1. rl=5 (cl=5, al=0) 2. dout n = data-out from column n 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes tras. min is satisfied at precharge command time (t5) and that trc. min is satisfied at the ne xt active command time (t10). t15 nop nop bl4 operation: command dqs, dqs# read bank a, row b t rtp t rp dq dqs, dqs# bl8 operation: t0 ck# ck address t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 pre nop nop act nop nop nop rl = al + cl dq do n d) n+2 do n+3 do n+4 do n+5 do n+6 do n+7 transitioning data don t care t11 t12 t13 t14 nop nop nop nop nop nop bank. col n bank a, (or all) do n do n+1 do n+1 do n+2 do n+3 note: 1. rl=5 (cl=5, al=0) 2. dout n = data-out from column n 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes tras. min is satisfied at precharge command time (t5) and that trc. min is satisfied at the ne xt active command time (t10). t15 nop nop bl4 operation: command dqs, dqs# read bank a, row b t rtp t rp dq dqs, dqs# bl8 operation: t0 ck# ck address t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 pre nop nop nop nop nop nop cl = 5 dq do n d) n+2 do n+3 do n+4 do n+5 do n+6 do n+7 transitioning data don t care t11 t12 t13 t14 nop nop nop nop act nop bank a, col n bank a, (or all) do n do n+1 do n+1 do n+2 do n+3 note: 1. rl = 8 (cl = 5, al = cl - 2) 2. dout n = data-out from column n 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. the example assumes tras. min is satisfied at pr echarge command time (t10) and that trc. min is satisfied at the n ext active command time (t15). t15 nop nop bl4 operation: command dqs, dqs# read bank a, row b al = cl ? 2 =3 t rtp dq dqs, dqs# bl8 operation: t rp
rev. 1.1 /jan. 2011 85 2.14. write operation 2.14.1 burst operation during a read or write command, ddr3 will suppor t bc4 and bl8 on the fly using address a12 during the read or write(auto precharge can be enabled or disabled). a12=0, bc4(bc4=burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column address. 2.14.2 write timing violations 2.14.2.1 motivation generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the dram works properly . however, it is desirable, for cert ain minor violations, that the dram is guaranteed not to ?hang up? and that erro rs are limited to that particular operation. for the following, it will be assumed that there are no timing violations with regard s to the write command itself (including odt, etc.) and that it does satisfy all timing requirements not mentioned below. 2.14.2.2 data setup and hold violations should the data to strobe timing requirements (tds, t dh) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with this write com- mand. in the example (figure 42 on page 87), the relevant strobe edges for write burst a are associated with the clock edges: t5,t5.5,t6,t6.5,t7,t7.5,t8,t8.5. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. 2.14.2.3 strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or the strobe to clock timing require- ments (tdss, tdsh, tdqss) be viol ated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subse- quent reads from that loca tion might result in unpredictable read data, however the dram will work properly otherwise. in the example (figure 50 on page 91) the relevant strobe edges for write burst n are associated with the clock edges: t4,t4.5,t5,t5.5,t6,t6.5,t7 ,t7.5,t8,t8.5 and t9. any timing r equirements starting or ending on one of these strobe edges need to be fulfilled for a valid burst. fo r write burst b the relevant edges are t8,t8.5,t9,t9.5,t10,t10.5, t11,t11.5,t12,t12.5 and t13. some e dges are associated with both bursts.
rev. 1.1 /jan. 2011 86 2.14.2.4 write timing parameters this drawing is for example only to enumerate the strobe edges that ?belong? to a write burst. no actual tim- ing violations are shown here. for a valid burst all timing parameters for each edge of a burst need to be sat- isfied (not only for one edge - as shown). figure 42. write timing definition and parameters note: 1. bl8, wl=5 (al=0, cwl=5) 2. din n = data-in from column n 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0[a1:0=00] or mr0[a1:0=] and a12=1 during write command at t0. 5. tdqss must be met at each rising clock edge. t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop dq2 din n transitioning data don t care write nop bank. col n din n+2 din n+3 wl=al+cwl tdqss(min) tdqsltdqsh tdqsltdqshtdqsltdqshtdqsltdqsh tdqsh(min) tdss tdss tdss tdss tdss tdqsl(min) tdqss tdsh tdsh tdsh twpst(min) din n+4 din n+6 din n+7 din n din n+2 din n+3 twpre(min) tdqsltdqsh tdqsltdqshtdqsltdqshtdqsltdqsh tdqsh(min) tdss tdss tdss tdss tdss tdqsl(min) twpst(min) din n+4 din n+6 din n+7 din n din n+2 din n+3 twpre(min) tdqsltdqsh tdqsltdqshtdqsltdqshtdqsltdqsh tdqsh(min) tdss tdss tdss tdss tdss tdqsl(min) tdqss tdsh tdsh tdsh twpst(min) din n+4 din n+6 din n+7 tdsh tdsh tdsh tdsh twpre(min) tdsh dqs, dqs# dq2 dqs, dqs# dq2 tdsh tdqss(nominal) tdqss(max) dm dm dm
rev. 1.1 /jan. 2011 87 2.14.3 write data mask one write data mask (dm) pin for each 8 data bits (d q) will be supported on ddr3 sdrams, consistent with the implementation on ddr2 sdrams. it has identical ti mings on write operations as the data bits as shown in figure 42, and though used in a unidirectional manner, is internally loaded identically to data bits to ensure matched system timing. dm is not used during read cycl es for any bit organizations including x4, x8, and x16, however, dm of x8 bit organization can be used as tdqs during write cycl es if enabled by the mr1[a11] set- ting. see 1.4.3.7 ?tdqs,tdqs? on page 16 for more details on tdqs vs. dm operations. 2.14.4 twpre calculation the method for calculating differential pulse widths for twpre is shown in figure 43. figure 43. method for calculating twpre transitions and endpoint 2.14.5 twpst calculation the method for calculating differential pulse widths for twpst is shown in figure 44. figure 44. method for calculating twpst transitions and endpoint ck ck resulting differential signal relevant for t wpre spectification vtt 0 v dqs - dqs twpre t1 twpre_begin t2 twpre_end ck ck resulting differential signal relevant for t wpst spectification vtt 0 v dqs - dqs t wpst t2 twpst_end t1 twpst_begin
rev. 1.1 /jan. 2011 88 figure 45. write burst operation wl=5 (al=0,cwl=5,bl8) figure 46. write burst operation wl=9 (al=cl-1,cwl=5,bl8) t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop twpre dq3 dout n write bank. col n dout n+5 dout n+6 dout n+7 dout n+1 dout n+2 dout n+3 dout n+4 wl=al+cwl twpst note: 1. bl=8, wl=5; cwl=5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during write command at t0. transitioning data don t care t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop twpre dq3 dout n write bank. col n dout n+1 dout n+2 dout n+3 note: 1. bl8, wl=9;al=(cl-1), cl=5, cwl=5. 2. din n=data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during write command at t0. transitioning data don t care cwl=5 al=4 wl=al+cwl
rev. 1.1 /jan. 2011 89 figure 47. write (bc4) to read (bc4) operation figure 48. write (bc4) to precharge operation t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 tn nop nop nop nop nop nop nop nop twpst dq2 wl=5 din n transitioning data don t care write nop bank. col n bank. col b din n+1 din n+2 din n+3 note: 1. bc4, wl=5, rl=5. 2. din n = data-in from column n; dout b= data-out form column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc=4 setting activated by mr0[a1:0= 10] during write command at t0 and read command at tn. 5. twtr controls the write to read delay to the same device and starts with the first rising clock edge after the las t write data shown at t7. read twrts5 twpre t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 tn nop nop nop nop nop nop nop nop twpst dq2 wl=5 din n transitioning data don t care write nop bank. col n din n+1 din n+2 din n+3 note: 1. bc4, wl=5, rl=5. 2. din n = data-in from column n; dout b= data-out form column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0=10] during write command at t0. 5. the write recovery time(twr) referenced from the first rising clock edge after the last write data shown at t7. twr specifies the last burst write cycle until the precharge command can be issued to the same bank. pre twr5 twpre
rev. 1.1 /jan. 2011 90 figure 49. write (bc4) otf to precharge operation figure 50. write (bl8) to write (bl8) address4 dqs, dqs# twpst dq2 din n transitioning data don t care bank. col n din n+1 din n+2 din n+3 note: 1. bc4 otf, wl=5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 otf setting activated by mr0[a1:0 = 01] and a12 = 0 during write command at t0. 5. the write recovery time(twr) starts at the rising clock edge t9 (4 clocks from t5). 4 clocks t0 ck# ck t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ta0 ta1 t14 command3 valid twr 5 wl = 5 twpre nop nop nop nop nop nop nop nop nop write nop nop nop nop nop t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop twpre twpst dq2 wl=5 din n transitioning data don t care t11 t12 t13 t14 write nop nop nop bank. col n din n+5 din n+6 din n+7 din n+1 din n+2 din n+3 din n+4 bank. col b twtr read rl=5 note: 1. rl=5 (cl=5, al=0), wl=5(cwl=5, al=0) 2. din n = data-in from column n; dout b= data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 during write command at t0. read command at t11 can be either bc4 or bl8 depending on mr0[a1:0] and a12 status at t13.
rev. 1.1 /jan. 2011 91 figure 51. write (bc4) to write (bc4) otf figure 52. write (bl8) to read (bc4/bl8) otf t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop nop twpre twpst dq2 wl=5 din n transitioning data don t care t11 t12 t13 t14 write nop nop nop bank. col n din n+1 din n+2 din n+3 bank. col b twtr read rl=5 note: 1. rl=5 (cl=5, al=0), wl=5 (cwl=5, al=0) 2. din n = data-in from column n; dout b= data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during write command at t0. read command at t11 can be either bc4 or bl8 depending on a12 status at t13. tbl= 4 clocks t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop twpre twpst dq2 wl=5 din n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 write nop nop nop nop write bank. col n tccd din n+5 din n+6 din n+7 din b din b+1 din n+1 din n+2 din n+3 din n+4 wl=5 note: 1. bl8, wl=5 (cwl=5, al=0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=00] or mr0[a1:0=01] and a12=1 duri ng write command at t0 and t4. bank. col b tbl=4 clocks twtr din b+4 din b+5 din b+6 din b+7 twr
rev. 1.1 /jan. 2011 92 figure 53. write (bc4) to read (bc4/bl8) otf figure 54. write (bc4) to read (bc4) t0 ck# ck o mmand3 a ddress4 q s, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop twpst dq2 wl=5 din n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 write nop nop nop nop write bank. col n bank. col b tccd din b din b+1 din n+1 din n+2 din n+3 wl=5 note: 1. bc4, wl=5 (cwl=5, al=0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during write command at t0 and t4. twpre tbl=4 clocks twr twtr twpre twpst address4 dqs, dqs# twpst dq2 din n transitioning data don t care bank. col n din n+1 din n+2 din n+3 note: 1. rl = 5 (cl =5, al = 0), wl=5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0[a1:0 = 10]. t0 ck# ck t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 command3 bank. col b twtr wl = 5 twpre nop nop nop nop nop nop nop nop nop write nop nop nop nop read rl = 5
rev. 1.1 /jan. 2011 93 figure 55. write (bl8) to write (bc4) otf figure 56. write (bc4) to write (bl8) otf t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop twpre twpst dq2 wl=5 din n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 write nop nop nop nop write bank. col n tccd din n+5 din n+6 din n+7 din b din b+1 din n+1 din n+2 din n+3 din n+4 wl=5 note: 1. wl=5 (cwl=5, al=0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0[a1:0=01] and a12=1 during write command at t0. bc4 setting activated by either mr0[a1:0=01] and a12=0 during write command at t4. bank. col b tbl=4 clocks twtr twr t0 ck# ck command3 address4 dqs, dqs# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop nop nop nop nop nop nop twpst dq2 wl=5 din n din b+2 din b+3 transitioning data don t care t11 t12 t13 t14 write nop nop nop nop write bank. col n bank. col b tccd din b din b+1 din n+1 din n+2 din n+3 wl=5 note: 1. wl=5 (cwl=5, al=0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0[a1:0=01] and a12=0 during write command at t0. bl8 setting activated by either mr0[a1:0=01] and a12=1 during write command at t4. twpre tbl=4 clocks twr twtr twpre twpst din b+6 din b+7 din b+4 din b+5
rev. 1.1 /jan. 2011 94 2.15 refresh command the refresh command (ref) is used during normal ope ration of the ddr3 sdrams. this command is non persistent, so it must be issued each time a refresh is required. the ddr3 sdram requires refresh cycles at an average periodic interval of trefi. when cs ,ras , and cas are held low and we high at the rising edge of the clock, the chip enters a refresh cycle. all ba nks of the sdram must be precharged and idle for a min- imum of the precharge time trp (min) before the refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during a refresh command. an internal address counter supplies the ad dresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refr esh command and the next valid command, except nop or des, must be greater than or equal to the minimum refresh cycle time trfc(min) as shown in figure 57. note that th e trfc timing parameter depends on memory density. in general, a refresh command needs to be issued to the ddr3 sdram regularly every trefi interval. to allow for improved efficiency in scheduling and swit ching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of 8 refres h commands can be postponed during operation of the ddr3 sdram, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are po stponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 x trefi (see figure 58). a maximum of 8 addi- tional refresh commands can be issued in advance (? pulled in?), with each one reducing the number of regu- lar refresh commands required later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maxi- mum interval between two surrounding refresh commands is limited to 9 x trefi (see figure 59). at any given time, a maximum of 16 ref commands can be issued within 2 x trefi. self-refresh mode may be entered with a maximum of eight refresh commands bein g postponed. after exiting self-refresh mode with one or more reresh commands postponed, additional refresh commands may be postponed to the extent that the total number of postponed refresh commands (before and after the self-refresh) will never exceed eight. during self-refresh mode, the number of postponed or pulled-in ref commands does not change. figure 57. refresh command timing time break don t care note: 1. only nop/des commands allowed after refresh command registered until trfe(min) expires. 2. time interval between two refresh commands may be extended to a maximum of 9 x trefi. t0 ck# ck t1 ta0 ta1 tb0 tb1 tb2 tb3 tc0 tc1 tc2 tc3 command trfc(min) nop nop nop ref nop ref ref valid valid valid valid valid valid valid valid trfc trefi (max. 9 x trefi) dram must be idle dram must be idle
rev. 1.1 /jan. 2011 95 figure 58. postponing refresh commands (example) figure 59. pulling-in re fresh commands (example) 9 x t refi 8 ref-commands postponed t refi t rfc t 9 x t refi 8 ref-commands postponed t refi t rfc t
rev. 1.1 /jan. 2011 96 2.16 self-refr esh operation the self-refresh command can be used to retain data in the ddr3 sdram, even if the rest of the system is powered down. when in the self-refresh mode, the ddr3 sdram retains data without external clocking. the ddr3 sdram device has a built-in timer to acco mmodate self-refresh operation. the self-refresh- entry (sre) command is defined by having cs , ras , cas , and cke held low with we high at the rising edge of the clock. before issuing the self-refresh-ent ry command, the ddr3 sdram must be idle with all bank precharge state with trp satisfied. also, on-die termination must be turned off before issuing self-refresh-entry com- mand, by either registering odt pin low ?odtl + 0.5tck ? prior to the self-refresh entry command or using mrs to mr1 command. once the self-refresh entry comma nd is registered, cke must be held low to keep the device in self-refresh mode. during normal operati on (dll on), mr1(a0=0), the dll is automatically dis- abled upon entering self-refresh and is automatically enabled (including a dll-reset) upon exiting self- refresh. when the ddr3 sdram has entered self-refresh mode , all of the external control signals, except cke and reset , are ?don?t care?. for proper self-refresh opera tion, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca and vrefdq) must be at valid levels. vrefdq supply may be tu rned off and vrefdq may take any value between vss and vdd during self-refresh operation, pr ovided that vrefdq is valid and stable prior to cke going back high and that fi rst write operation or first write leveling activity may not occur earlier than 512 nck after exit from self-refresh. the dram initiates a minimum of one refresh command internally within tcke period once it enters sell-refresh mode. t he clock is internally disabled during self-refresh op eration to save power. the minimum time that the ddr3 sdram must remain in self-r efresh mode is tckesr. the user may change the external clock fre- quency or halt the external clock tcksre after self-ref resh entry is registered, however, the clock must be restarted and stable tcksrx before the device can exit self-refresh operation. the procedure for exiting self-refresh requires a sequenc e of events. first, the clock must be stable prior to cke going back high. once a self-ref resh exit command (srx, combination of cke going high and either nop or deselect on command bus) is registered, a delay of at least txs must be satisfied before a valid com- mand not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a delay of at least txsdll and applicable zqcal function requirements (tbd) must be satisfied. before a command that requires a locked dll can be ap plied, a delay of at least txsdll must be satisfied. depending on the system environment and the amount of time spent in self-refresh, zq calibration com- mands may be required to compensate for the voltage and temperature drift as described in ?zq calibration commands? on page 76. to issue zq calibration comma nds, applicable timing requirements must be satis- fied (see figure 74 - ?zq calibration timing? on page 108). cke must remain high for th e entire self-refresh exit period txsdll for proper operation except for self- refresh re-entry. upon exit from self-refresh, the dd r3 sdram can be put back into self-refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval txs. odt must be turned off during txsdll.
rev. 1.1 /jan. 2011 97 figure 60. self-refresh entry/exit timing t0 t1 ck ck# cke odt addr t2 ta0 tb0 tc0 tc1 tcksre td0 te0 tf0 valid valid valid nop sre nop nop(1) valid(2) valid(3) srx command valid valid tcpded tis tcksrx tckesr tis odtl trp txs txsdll enter self refresh exit self refresh don?t care time break notes: 1. only nop or des command. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll.
rev. 1.1 /jan. 2011 98 2.17 power-down modes 2.17.1 power-down entry and exit power-down is synchronously entered when cke is registered low (alo ng with nop or deselect command). cke is not allowed to go low while mode register set command, mpr operations, zqcal operations, dll locking or read / write operation are in progress. cke is allowed to go low while any of other operations such as row activation, precharge or aut o-precharge and refresh are in prog ress, but power-down idd spec will not be applied until finishing those operations. timing diag rams are shown in figures 61 through figures 73 with details for entry and exit of power-down. the dll should be in a locked state when power-down is entered for fastest powe r-down exit timing. if the dll is not locked during power-down entry, the dll must be reset after exiting power-down mode for proper read operation and synchronous od t operation. dram design provides all ac and dc timing and voltage specification as well as proper dll operation with any cke intensive operations as long as dram controller complies with dram specifications. during power-down, if all banks ar e closed after any in-progress comma nds are completed, the device will be in precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in acti ve power-down mode. entering power-down deactivates the inpu t and output buffers, excluding ck, ck , odt, cke and reset . to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycle(s) after, this timing period are defined as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. also , the dll is disabled upon entering precharge power-down (slow exit mode) , but the dll is kept enabled during precharge power-down (fast exit mode) or ac tive power-down. in powe r-down mode, cke low, reset high and a stable clock signal must be main tained at the inputs of the ddr3 sdram, and odt should be in a valid state, but all other input signals are ?don?t care? (if reset goes low during power-down, the dram will be out of pd mode and into reset state . ) cke low must be maintain ed until tcke has been sat- isfied. power-down durati on is limited by 9 times trefi of the device. the power-down state is synchronou sly exited when cke is registered high (along with a nop or deselect command). cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power-down exit latency, txp and/or txpdll after cke goes high. power-down exit latency is defined in the ac specificati ons table of this data sheet. active power down entry and exit timing diagram example is shown in figure 61. timing diagrams for cke with pd entry, pd exit with read and read with auto precharge, write, write with auto precharge, activate, precharge, refresh, and mrs are shown in figure 62 thr ough figure 70. additional clarifications are shown in figure 71through figure 73. table 22. power-down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don?t care on fast txp to any valid command precharged (all banks precharged) 0offslow txp to any valid command. since it is in precharge state, commands here w ill be act,ref,mrs,pre or prea. txpdll to commands that need the dll to operate, such as rd,rda or odt control line. precharged (all banks precharged) 1onfast txp to any valid command.
rev. 1.1 /jan. 2011 99 figure 61. active power-down entry and exit timing diagram figure 62. power-down entry after read with auto precharge t0 t1 ck ck# cke address t2 ta0 ta 1 t b 0 t b 1 tc 0 valid valid valid valid tpd tis tcpded txp enter exit don?t care time break valid nop nop valid command nop nop nop tih tis tih tcke power-down mode power-down mode note: valid command at t0 is act, nop, des or pre with still on bank remaining open after completion of the precharge command. t0 t1 ck ck# oke dqs, dqs# ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ta 6 ta 7 address tckesr tis trdpden tpd power-down transitioning data time break ta 8 t b 0 t b 1 rd or nop nop nop nop valid command nop nop nop nop nop nop nop rda valid valid tis tcpded d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 d in b d in b+1 d in b+2 d in b+3 dq bl8 dq bc4 valid entry don?t care
rev. 1.1 /jan. 2011 100 figure 63. power-down entry after write with auto precharge figure 64. power-down entry after write t0 t1 ck ck# oke dqs, dqs# ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ta 6 ta 7 address twrapden tpd power-down tb0 tb1 tb2 nop nop nop nop valid command nop nop nop nop nop nop nop write bank, tis tcpded d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 d in b d in b+1 d in b+2 d in b+3 dq bl8 dq bc4 entry tc0 tc1 valid valid col n valid valid a10 wl=al+cwl start internal precharge transitioning data time break don?t care note: 1. twr is programmed through mr0. wr(1) t0 t1 ck ck# oke dqs, dqs# ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ta 6 ta 7 address twrapden tpd power-down tb0 tb1 tb2 nop nop nop nop valid command nop nop nop nop nop nop nop write bank, tis tcpded d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 d in b d in b+1 d in b+2 d in b+3 dq bl8 dq bc4 entry tc 0 tc1 valid valid col n valid valid a10 wl=al+cwl twr transitioning data time break don?t care
rev. 1.1 /jan. 2011 101 figure 65. precharge power-down (fast exit mode) entry and exit figure 66. precharge power-down (slow exit mode) entry and exit t0 t1 ck ck# cke t2 ta0 ta1 t b0 t b1 tc 0 valid valid tcpded tis tpd enter exit don?t care time break nop nop valid command nop nop nop tis tih txp power-down mode power-down mode t0 t1 ck ck# cke t2 ta0 ta 1 t b 0 t b 1 tc 0 valid tcpded tis tpd enter exit don?t care time break nop nop command nop nop nop tis tih txp power-down mode power-down mode td0 valid valid valid valid txpdll
rev. 1.1 /jan. 2011 102 figure 67. refresh command to power-down entry figure 68. active comma nd to power-down entry t0 t1 ck ck# cke t2 t3 ta 0 ta 1 valid tis trefpden don?t care time break ref nop command nop nop valid valid valid tcpded tpd address t0 t1 ck ck# cke t2 t3 ta 0 ta 1 valid tis tactpden don?t care time break active nop command nop nop valid valid valid tcpded tpd address
rev. 1.1 /jan. 2011 103 figure 69. precharge/precharge all command to power-down entry figure 70. mrs command to power-down entry t0 t1 ck ck# cke t2 t3 ta 0 ta 1 valid tis tprepden don?t care time break pre or nop command nop nop valid valid valid tcpded tpd address prea t0 t1 ck ck# cke ta 0 ta 1 tb0 tb1 valid tis tmrspden don?t care time break nop command nop valid valid valid tcpded tpd address nop mrs
rev. 1.1 /jan. 2011 104 2.17.2 power-down clar ifications - case 1 when cke is registered low for power-down entry, tp d (min) must be satisfied before cke can be registered high for power-down exit. the minimum value of para meter tpd (min) is equal to the minimum value of parameter tcke(min) as shown in table 52, timing parameters by speed bin. a detail example of case 1 is shown figure 71. figure 71. power-down entry/ exit clarifications - case1 2.17.3 power-down clar ifications - case 2 for certain cke intensive operations, for example, repeated ?pd exit - re fresh - pd entry? sequences, the number of clock cycles between pd exit and pd entry may be insufficient to keep the dll updated. there- fore the following conditions must be met in addition to tcke in order to maintain proper dram operation when the refresh command is issued between pd exit and pd entry. power-down mode can be used in con- junction with the refresh command if the following conditions are met: 1) txp must be satisfied before issuing the command. 2) txpdll must be sa tisfied (referenced to th e registration of pd exit) before the next power- down can be entered. a detailed example of case 2 is shown in figure 72. figure 72. power-down entry/ exit clarifications - case2 t0 t1 ck ck# cke t2 ta0 ta 1 t b 0 tis don?t care time break nop command valid tcpded address nop valid tb1 tb2 nop nop nop nop tih tis tih tis tpd tcke tcpded enter exit power-down mode power-down mode enter power-down mode tpd t0 t1 ck ck# cke t2 ta0 ta 1 t b 0 tis don?t care time break nop command valid tcpded address nop valid tb1 tc0 nop nop nop tih tis tih tcke txp enter exit power-down mode power-down mode enter power-down mode tc 1 t d 0 nop ref nop tpd txpdll
rev. 1.1 /jan. 2011 105 2.17.4 power-down clar ifications - case 3 if an early pd entry is issued after a refresh command , once pd exit is issued, nop or des with cke high must be issued until trfc(min) from the refresh comma nd is satisfied. this means cke can not be regis- tered low twice within a trfc(min) window. a deta iled example of case 3 is shown in figure 73. figure 73. power-down entry/ exit clarifications - case3 t0 t1 ck ck# cke t2 ta0 ta 1 t b 0 tis don?t care time break nop command tcpded address nop ref tb1 tc0 nop nop nop tih tis tih tcke txp enter exit power-down mode power-down mode enter power-down mode tc 1 t d 0 valid nop nop tpd trfc(min) valid valid
rev. 1.1 /jan. 2011 106 2.18 zq calibration commands 2.18.1 zq calibration description zq calibration command is used to calibrate dram ron & odt values. ddr3 sdram needs longer time to calibrate output driver and on-die termination circuits at initialization and relative ly smaller time to perform periodic calibrations. zqcl command is used to perform the initial calibration duri ng power-up initializat ion sequence. this com- mand may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and, once calibration is achieved, the calibrated values are transferred from the calibration engi ne to dram io, which gets reflected as updated output driver and on-die termination values. the first zqcl command issued after reset is allowed a ti ming period of tzqinit to perform the full calibration and the transfer of values . all other zqcl commands except the fi rst zqcl command issued after reset are allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibra tion and transfer of valu es as defined by timing parameter tzqcs.one zqcs command can effectively correct a minimum of 0.5%(zqcorrection) of ron and rtt impedance error within 64 nck for all speed bi ns assuming the maximum se nsitivities specified in the ?output driver voltage and temperature sensitivit y? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs comm ands can be determined from these tables and other application-specific parameters. one method for calc ulating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift ra tes that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max (drttdt, drondtm) and vsens = max (drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ , vsens = 0.15%/mv, tdriftrate = 1 /sec and vdriftrate = 15mv/sec, then the interval between zqcs commands is calculated as: no other activities should be performed on the dram channel by the controller for the duration of tzqinit, tzqoper, or tzqcs. the quiet time on the dram channel allows accurate calibration of output driver and on-die termination values. once dram calibration is achieved, the dram should di sable zq current consumption path to reduce power. all banks must be precharged and trp met before zq cl or zqcs commands are issued by the controller. sea table 14 ?command truth table? on page 50 for a description of the zqcl and zqcs commands. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self-refresh exit, ddr3 sdra m will not perform an io calibration without an explicit zq calibration command. the earliest possible time fo r zq calibration command (short or long) after self refresh exit is txs. in systems that share the zq resistor between devices, the controller must not allow any overlap of tzqoper , tzqinit or tzqcs between the devices. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 128 ms
rev. 1.1 /jan. 2011 107 2.18.2 zq calibration timing figure 74. zq calibration timing 2.18.3 zq external resi stor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm+/- 1% tolerance external resistor must be connected between the zq pin and ground. the single resistor can be used fo r each sdram or one resistor can be shared between two sdrams if the zq calibration timings for each sdram do not overlap. the total capacitive loading on the zq pin must be limited (see ?input / output ca pacitance? on each datasheet). t0 t1 ck ck# ta 0 ta 1 ta 2 ta 3 tb0 tb1 tc 0 tc1 tc2 cke zqcl nop nop nop valid valid nop nop nop nop valid command address (1) valid valid valid valid valid valid valid valid valid odt (2) valid valid valid a10 (1) (2) dq bus (3) hi-z activities hi-z (3) activities tzqinit or tzqoper tzqcs time break don?t care note: 1. cke must be continuously register ed high during the calibration procedure. 2. on-die termination must be disabled via the odt signal or mrs during the calibration procedure. 3. all devices connected to the dq bus should be high impedance during the calibration procedure.
rev. 1.1 /jan. 2011 108 3. on-die termination (odt) odt (on-die termination) is a feature of the ddr3 sdram that allows the dram to turn on/off termination resistance for each dq, dqs, dqs and dm for x4 and x8 configuration (and tdqs, tdqs for x8 configura- tion, when enabled via a11=1 in mr1) via the odt control pin. for x16 configuration , odt is applied to each dqu, dql, dqsu, dqsu , dqsl, dqsl , dmu and dml signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory ch annel by allowing the dram controller to independently turn on/off termination resistance for any or all dr am devices. more details about odt control modes and odt timing modes can be found fu rther down in this document: ? the odt control modes are described in 3.1. ? the odt synchronous mode is described in 3.2. ? the dynamic odt feature is described in 3.3. ? the odt asynchronous mode is described in 3.4 ? the transitions between odt synchronous and asynchronous are described in 3.4.1 through 3.4.4 the odt feature is turned off and not supported in self-refresh mode. a simple functional representation of th e dram odt feature is shown in figure 75. figure 75. functional representation of odt the switch is enabled by the internal odt control logi c, which uses the external odt pin and other control information, see below. the value of r tt is determined by the settings of mode register bits (see figure 9 on page 44 and figure 10 on page 47 ). the odt pin will be ignored if the mode register mr1 and mr2 are programmed to disable odt and in self-refresh mode. 3.1 odt mode register and odt truth table the odt mode is enabled if either of mr1 {a9, a6 , a2} or mr2 {a10, a9} are non zero. in this case , the value of rtt is determined by the settings of those bits (see figure 9 on page 44). application: controller sends wr co mmand together with odt asserted. ? one possible application: the rank that is being written to provides termination. ? dram turns on termination if it sees odt asserted (except odt is disabled by mr). ? dram does not use any write or read command decode information. ? the termination truth table is shown in table 23. odt vddq/2 rtt switch dq, dqs, dm, tdqs to other circuitry like rcv, ...
rev. 1.1 /jan. 2011 109 3.2 synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power-down definition, these modes are: ? any bank active with cke high ? refresh with cke high ? idle mode with cke high ? active power down mode (regardless of mr0 bit a12) ? precharge power down mode if dll is enable d during precharge power down by mr0 bit a12. the direct odt feature is not supported during dll-of f mode. the on-die termination resistors must be dis- abled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll-off mode. in synchronous odt mode, r tt will be turned on odtlon clock cycles af ter odt is sampled high by a rising clock edge and turned off od tloff clock cycles after odt is register ed low by a rising clock edge. the odt latency is tied to the write latency (wl) by: odtlon = wl - 2; odtloff = wl -2. 3.2.1 odt latency and posted odt in synchronous odt mode, the additive latency (al) programmed into the mode register (mr1) also applies to the odt signal. the dram internal odt signal is delayed for a number of clock cycles defined by the additive latency (al) relative to the external odt signal. odtlon = cwl + al - 2; odtloff = cwl + al - 2. for details, refer to odt timing parameters listed in table 52 on page 150 and table 53 on page 159. 3.2.2 timing parameters in synchronous odt mode, the following timing parameters apply (see also figure 76): odtlon, odtloff , t aon,min,max , t aof,min,max . minimum rtt turn-on time ( t aon min) is the point in time when the de vice leaves high impedance and odt resistance begins to turn on. maximum rtt turn on time ( t aon max) is the point in time when the odt resistance is fully on. both are measured from odtlon. minimum rtt turn-off time ( t aof min) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time ( t aof max) is the point in time when the on-die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write co mmand is registered by the sdram with odt high, then odt must remain high until odth4 (bl = 4) or odth8 (bl = 8) after the write command (see figure 77). odth4 and odth8 are meas ured from odt registered high to odt registered low or from the registration of a writ e command until odt is registered low. table 23. termination truth table odt pin dram termination state 0off 1 on, (off, if disabled by mr1 {a9, a6, a2} and mr2 {a10, a9} in general)
rev. 1.1 /jan. 2011 110 figure 1. figure 76. synchronous odt timing example for al=3; cwl=5; odtlon = al+cwl-2=6.0; odtloff = al+cwl-2=6 figure 77. synchronous odt example with bl=4, wl=7 t0 t1 ck ck# cke t2 t3 t4 t5 dram_rtt t6 t7 al=3 odth4, min taonmin t8 t9 t10 t11 t12 t13 t14 t15 al=3 cwl-2 odt odtlon = cwl+al-2 odtloff = cwl+al-2 taonmax rtt_nom taofmax taofmin transitioning don??t care t0 t1 ck ck# cke t2 t3 t4 t5 dram_rtt t6 t7 taonmin t8 t9 t10 t11 t12 t13 t14 t15 odth4min odth4 odt odtloff = wl-2 taonmax rtt_nom taofmax taofmin t16 t17 nop nop nop nop nop nop nop wrs4 nop nop nop nop nop nop nop nop nop nop odth4 odtloff = wl-2 odtlon = wl-2 odtlon = wl-2 command taofmax taonmin taonmax taofmin transitioning don?t care
rev. 1.1 /jan. 2011 111 odt must be held high for at least odth4 after assert ion (t1); odt must be kept high odth4 (bl = 4) or odth8 (bl = 8) after write command (t7). odth is meas ured from odt first registered high to odt first registered low, or from registration of write comma nd with odt high to odt registered low. note that although odth4 is satisfied from od t registered high at t6, odt must not go low before t11 as odth4 must also be satisfied from the regi stration of the write command at t7. 3.2.3 odt during reads as the ddr3 sdram can not terminate and drive at the same time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may not be enabled until the end of the post-amble as shown in the example belo w. as shown in figure 78 below at cycle t15, dram turns on the termination when it stops driving, which is determined by thz. if dram stops driving early (i.e., thz is early), then taonmin timing may apply. if dram st ops driving late (i.e., thz is late), then dram com- plies with taonmax timing. note that odt may be disabl ed earlier before the read and enabled later after the read than shown in this example in figure 78. figure 78. odt must be disabled externally du ring reads by driving odt low. (example: cl=6; al=cl-1=5; rl=al+cl=11; cwl=5; odtlo n = cwl+al-2=8; odtloff = cwl+al-2=8) t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 taofmin t8 t9 t10 t11 t12 t13 t14 t15 odtlon = cwl+al-2 odt rtt_nom taonmax t16 t17 read nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop odtloff = cwl+al-2 command transitioning don?t care address valid rtt rtt_nom d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 dq rl=al+cl taofmax
rev. 1.1 /jan. 2011 112 3.3 dynamic odt in certain application cases and to further enhance signal in tegrity on the data bus, it is desirable that the ter- mination strength of the ddr3 sdram can be changed without issuing an mrs command. th is requirement is supported by the ?dynamic odt? feature as described as follows: 3.3.1 functional description: the dynamic odt mode is enabled if bit (a 9) or (a10) of mr2 is set to ?1?. the function is described as follows: ? two rtt values are availa ble: rtt_nom and rtt_wr. ? the value for rtt_nom is preselected via bits a[9,6,2] in mr1 . ? the value for rtt_wr is preselected via bits a[10,9] in mr2 . ? during operation without write commands, th e termination is controlled as follows: ? nominal termination strength rtt_nom is selected. ? termination on/off timing is controlled via odt pin and latencies odtlon and odtloff. ? when a write command (wr, wra, wrs4, wrs8, wr as4, wras8) is register ed, and if dynamic odt is enabled, the termination is controlled as follows: ? a latency odtlcnw after the write command, termination strength rtt_wr is selected. ? a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, te rmination strength rtt_nom is selected. ? termination on/off timing is controlle d via odt pin and odtlon, odtloff. table 25 shows latencies and timing parameters which are relevant for the on-die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll-of f mode. user must use mrs command to set rtt_wr, mr2{a10, a9}={0,0}, to dis able dynamic odt externally. when odt is asserted, it must remain high until odth4 is satisfied. if a write co mmand is registered by the sdram with odt high, then odt must remain high until odth4 (bl = 4) or odth8 (bl = 8) after the write command (see figure 77). odth4 and odth8 are meas ured from odt registered high to odt registered low or from the registration of a writ e command until odt is registered low. table 24. latencies and timing parameters relevant for dynamic odt name and description abbr. defined from defined to definition for all ddr3 speed bins unit odt turn-on latency odtlon registering external odt signal high turning termination on odtlon = wl - 2 t ck odt turn-off la tency odtloff registering external odt signal low turning termination off odtloff = wl - 2 t ck odt latency for changing from rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw = wl - 2 t ck odt latency for change from rtt_wr to rtt_nom(bl=4) odtlcwn4 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn4= 4+odtloff t ck odt latency for change from rtt_wr to rtt_nom(bl=8) odtlcwn8 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn8= 6+odtloff t ck (avg)
rev. 1.1 /jan. 2011 113 3.3.2 odt timing diagrams the following pages provide exemplary timing diagrams as described in table 25: table 24. latencies and timing parameters relevant for dynamic odt (cont?d) note: taof, nom and tadc,nom are 0.5 tck (effectively adding half a clock cycle to odtloff, odtcnw and odtlcwn) name and description abbr. defined from defined to definition for all ddr3 speed bins unit minimum odt high time after odt assertion odth4 registering odt high odt registered low odth4 = 4 t ck (avg) minimum odt high time after write (bl = 4) odth4 registering write with odt high odt registered low odth4 = 4 t ck (avg) minimum odt high time after write (bl = 8) odth8 registering write with odt high odt registered low odth8 = 6 t ck (avg) rtt change skew tadc odtlcnw odtlcwn rtt valid tadc(min)=0.3*tck(avg) tadc(max)=0.7*tck(avg) t ck (avg) table 25. timing diagrams for ?dynamic odt? figure and page description figure 79 on page 114 figure 79, dynamic odt: behavior with odt being asserted before and after the write. figure 80 on page 114 figure 80, dynamic odt: behavior without write command, al = 0, cwl = 5. figure 81 on page 115 figure 81, dynamic odt: behavior with od t pin being asserted together with write command for a duration of 6 clock cycles. figure 82 on page 115 figure 82, dynamic odt: behavior with od t pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al = 0, cwl = 5. figure 83 on page 116 figure 83, dynamic odt: behavior with od t pin being asserted together with write command for a duration of 4 clock cycles.
rev. 1.1 /jan. 2011 114 figure 79. dynamic odt: behavior with odt being asserted before and after the write figure 80. dynamic odt: behavior without write command, al=0, cwl=5 t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 odtloff odt t16 t17 nop nop nop nop wrs4 nop nop nop nop nop nop nop nop nop nop nop nop nop odth4 command transitioning don?t care address rtt d in b d in b+1 d in b+2 d in b+3 dq odtlcnw valid odth4 taonmin taonmax rtt_nom tadcmin tadcmax odtlon odtlown4 rtt_wr taofmin taofmax rtt_nom wl note: example for bc4 (via mrs or otf), al=0, cwl=5. odth4 applie s to first registering odt high and to the registration of the write command. in this example, odth4 would be satisfied if od t went low at t8(4 clocks after the write command). tadcmin tadcmax t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 t8 t9 t10 t11 odtloff odt valid valid valid valid valid valid valid valid valid valid valid valid odth4 command transitioning don?t care address rtt dq odtlon taonmax taonmin rtt_nom taofmin taofmax odtlown4 note: odth4 is defined from odt registered high to odt re gistered low, so in this example, odth4 is satisfied. odt registered low at t5 would also be legal.
rev. 1.1 /jan. 2011 115 figure 81. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles figure 82. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al=0, cwl=5. t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 tadcmax t8 t9 t10 t11 odtloff odt nop wrs8 nop nop nop nop nop nop nop nop nop nop odth8 command transitioning don?t care address rtt d in b d in b+1 d in b+2 d in b+3 d in b+4 d in b+5 d in b+6 d in b+7 dq odtl=8 taonmin valid odtlcnw odtlon taofmin taofmax rtt_wr wl note: example for bl8 (via mrs or otf), al=0, cwl=5. in this example, odth8=6 is exactly satisfied. t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 tadcmax t8 t9 t10 t11 odtloff odt nop wrs4 nop nop nop nop nop nop nop nop nop nop odth4 command transitioning don?t care address rtt d in b d in b+1 d in b+2 d in b+3 dq odtlcwn4 taonmin valid odtlcnw taofmin taofmax rtt_wr wl odtlon tadcmin tadcmax rtt_nom note: odth4 is defined from odt registered high to odt re gistered low, so in this example, odth4 is satisfied. odt registered low at t5 would also be legal.
rev. 1.1 /jan. 2011 116 figure 83. dynamic odt: behavior with odt pin being asserted together with write command for a duration of 4 clock cycles t0 t1 ck ck# t2 t3 t4 t5 dqs,dqs# t6 t7 tadcmax t8 t9 t10 t11 odtloff odt nop wrs4 nop nop nop nop nop nop nop nop nop nop odth4 command address rtt d in b d in b+1 d in b+2 d in b+3 dq odtlcwn4 taonmin valid odtlcnw rtt_wr wl odtlon taofmin taofmax transitioning don?t care note: example for bc4 (via mrs or otf), al=0, cwl=5. in this example, odth=4 is exactly satisfied.
rev. 1.1 /jan. 2011 117 3.4 asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporarily disabled (i.e. frozen) in precharge power-down (by mr0 bit a12). based on the power down mode definitions, this is currently (comment: update editorially after everything is set and done...): precharge power down mode if dll is disabled during precharge power down by mr0 bit a12. in asynchronous odt timing mode, internal odt comman d is not delayed by additive latency (al) relative to the external odt command. in asynchronous odt mode, the following timing parameters apply (see figure 84): t aonpd,min,max , t aofpd,min,max . minimum rtt turn-on time ( t aonpd min) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maximum rtt turn on time ( t aonpd max) is the point in time when the odt resistance is fully on. t aonpd min and t aonpd max are measured from odt being sampled high. minimum rtt turn-off time ( t aofpd min) is the point in time when the devi ces termination circuit starts to turn off the odt resistance. maxi mum odt turn off time ( t aofpd max) is the point in time when the on-die termina- tion has reached high impedance. t aofpd min and t aofpd max are measured from odt being sampled low. figure 84. asynchronous odt timings on ddr3 sdra m with fast odt transition: al is ignored in precharge power down, odt receiver remains active, however no read or write command can be issued, as the respective add/cmd receivers may be disabled. t0 t1 ck ck# cke t2 t3 t4 t5 rtt t6 t7 taonpd min t8 t9 t10 t11 t12 t13 t14 t15 odt taonpdmax t16 t17 transitioning don?t care tih tis tih tis taofpdmin taofpdmax rtt table 26. asynchronous odt timings parameters for all speed bins symbol description min max unit t aonpd asynchronous rtt turn-on delay (power-down with dll frozen) 2 8.5 ns t aofpd asynchronous rtt turn-off delay (power-down with dll frozen) 2 8.5 ns
rev. 1.1 /jan. 2011 118 3.4.1 synchronous to asynchr onous odt mode transitions 3.4.2 synchronous to asyn chronous odt mode transi tion during power-down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to ?0?, there is a transition period around power down entry, wher e the ddr3 sdram may show either synchronous or asynchronous odt behavior. the transition period is defined by the parameters tanpd and tcpded(min ). tanpd is equal to (wl-1) and is counted backwards in time from the clock cycle where c ke is first registered low. tcpded(min) starts with the clock cycle where cke is first register ed low. the transition period begins with the starting point of tanpd and terminates at the end point of tcpded(min) as shown in figure 85. if there is a refresh command in progress while cke goes low, then the transition period ends at the later one of trfc(min) after the refresh command and the end point of tcpded (min) as shown in figure 86 . please note that the actual starting point at tanpd is excluded from the transition period, and the actual end points at tcpded(min) and trfc(min), respectively, are included in the transition period. odt assertion during the transition period may result in an rtt change as early as the smaller of t aonpd min and (odtlon*t ck +t aon min) and as late as the larger of t aonpd max and (odtlon*t ck +t aon max). odt de-assertion during the transition period may result in an rtt change as early as the smaller of t aofpd min and (odtlof*t ck +t aof min) and as late as the larger of t aofpd max and (odtloff*t ck +t aof max). see figure 18 and figure 85. note that, if al has a large value, the range where rtt is uncertain becomes quite large. figure 85 sh ows the three different cases: odt_a, synchronous behavior before tanpd; odt_b has a state change during the transition period; odt_c shows a state change after the transition period. table 27. odt timing parameters for power down (w ith dll frozen) entry and exit transition period description min max odt to rtt turn-on delay min {odtlon * tck + taonmin; taonpdmin} max {odtlon * tck + taonmax; taonpdmax} min {(wl-2) * tck + taonmin; taonpdmin} min {(wl-2) * tck + taonmax; taonpdmax} odt to rtt turn-off delay min {odtloff * tck + taofmin; taofpdmin} min {odtloff * tck + taofmax; taofpdmax} min {(wl-2) * tck + taofmin; taofpdmin} min {(wl-2) * tck + taofmax; taofpdmax} tanpd wl-1
rev. 1.1 /jan. 2011 119 figure 85. synchronous to asynchronous transition during precharge power down (with dll frozen) entry (al=0; cwl=5; tanpd = wl-1=4) t0 t1 ck ck# cke t2 t3 t4 t5 first async. odt t6 t7 tanpd t8 t9 t10 t11 t12 tcpded transitioning don?t care nop nop nop nop nop nop nop nop nop nop nop command tcpdedmin pd entry transition period last sync. odt rtt taofmin taofmax taofpdmax sync or async. odt rtt odtloff + taofmin rtt taofpdmin odtloff + taofmax rtt rtt taofpdmin pd entry transition period rtt taofpdmax odtloff
rev. 1.1 /jan. 2011 120 figure 86. synchronous to asynchronous transi tion after refresh command (al=0; cwl=5; tanpd = wl-1=4) t0 t1 ck ck# t2 t3 t4 t5 sync, or async. odt t6 t7 t8 t9 t10 t11 t12 t13 ta0 ta 1 last sync.odt ta 2 ta 3 nop ref nop nop nop nop nop nop nop command transitioning don?t care rtt taofmin taofmax cke trfc(min) tanpd tcpdedmin pd entry transition period rtt odtloff odtloff + taofpdmin taofpdmax taofpdmin rtt odtloff + taofpdmax rtt taofpdmin rtt taofpdmax rtt first async. odt
rev. 1.1 /jan. 2011 121 3.4.3 asynchronous to synchronous odt mo de transition during power-down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to ?0?, there is also a transition period around power down exit, wher e either synchronous or asynchronous response to a change in odt must be expected from the ddr3 sdram. this transition period starts tanpd before cke is first registered high, and ends txpdll after cke is first registered high. tanpd is equal to (wl - 1) and is count ed (backwards) from the clock cycle where cke is first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of t aonpd min and (odtlon*t ck +t aon min) and as late as the larger of t aonpd max and (odtlon*t ck +t aon max). odt de- assertion during the transition period may result in an rtt change as early as the smaller of t aofpd min and (odtloff *t ck +t aof min) and as late as the larger of t aofpd max and (odtloff*t ck +t aof max). see table 27. note that, if al has a large value, the range where rtt is uncertain becomes quite large. figure 87 shows the three different cases: odt_c, asynchronous response before t anpd ; odt_b has a state change of odt during the transition period; odt_a shows a state c hange of odt after the transition period with synchro- nous response. figure 87. asynchronous to synchronous transition during precharge power down (with dll frozen) exit (cl=6; al=cl-1; cwl=5; tanpd = wl - 1=9) t0 t1 ck ck# t2 ta0 ta 1 ta 2 sync, or async. odt ta 3 ta 4 ta 5 ta 6 tb0 tb1 tb2 tc0 tc1 tc 2 last sync. odt td0 td1 nop nop nop nop nop nop nop nop nop command rtt taofpdmin taofpdmax cke tanpd txpdll pd entry transition period rtt odtloff + taofmin taofpdmax taofpdmin rtt odtloff + taofmax rtt taofmin rtt taofmax rtt first async. odt nop nop nop nop nop odtloff transitioning don?t care
rev. 1.1 /jan. 2011 122 3.4.4 asynchronous to synchronous odt mo de during short ck e high and short cke low periods if the total time in precharge power down state or idle state is very short, the tran sition periods for pd entry and pd exit may overlap (see figure 88). in this case , the response of the ddr3 sdrams rtt to a change in odt state at the input may be synch ronous or asynchronous from the start of the pd entry transition period to the end of the pd exit transition period (even if the entry period ends later than the exit period). if the total time in idle state is very short, the transition periods for pd exit and pd entry may overlap. in this case the response of the ddr3 sd rams rtt to a change in odt stat e at the input may be synchronous or asynchronous from the start of the pd exit transition pe riod to the end of the pd entry transition period. note that in the bottom part of figure 88 it is assumed t hat there was no refresh command in progress when idle state was entered. figure 88. transition period for short cke cycles, entry and exit period overlapping (al=0, wl=5, tanpd = wl-1=4) t0 t1 ck ck# t2 t3 t4 t5 t6 t7 tanpd t8 t9 t10 t11 t12 t13 t14 cke transitioning don?t care ref nop command nop nop nop nop nop nop nop nop nop nop nop nop nop cke trfc (min) pd entry transition period pd exit transition period tanpd txpdll short cke low transition period tanpd short cke high transition period txpdll
rev. 1.1 /jan. 2011 123 4. ac & dc input measurement levels 4.1 ac and dc logic input levels for single-ended signals 4.1.1 ac and dc input levels for si ngle-ended command and address signals table 28. single-ended ac and dc input levels for command and address symbol parameter min max unit notes vih.ca(dc100) dc input logic high vref + 0.100 vdd v 1, 5 vil.ca(dc100) dc input logic low vss vref - 0.100 v 1, 6 vih.ca(ac175) ac input logic high vref + 0.175 note 2 v 1, 2, 7 vil.ca(ac175) ac input logic low note 2 vref - 0.175 v 1, 2, 8 vih.ca(ac150) ac input logic high vref + 0.150 note 2 v 1, 2, 7 vil.ca(ac150) ac input logic low note 2 vref - 0.150 v 1, 2, 8 v refca(dc ) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 notes: 1. for input only pins except reset , vref = vrefca(dc). 2. see ?$paratext>? on page 135. 3. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. 5. vih(dc) is used as a simplified symbol for vih.ca(dc100) 6. vil(dc) is used as a simplif ied symbol for vil.ca(dc100) 7. vih(ac) is used as a simplified symbol for vih.ca(ac175) and vih. ca(ac150); vih.ca(ac175) value is used when vref+0.175v is referenced and vih.ca(a c150) value is used when vref+0.150v is refer- enced. 8. vil(ac) is used as a simplified symbol for vil.ca (ac175) and vil.ca(ac150); vil.ca(ac175) value is used when vref-0.175v is referenc ed and vil.ca(ac150) value is us ed when vref-0.150v is referenced.
rev. 1.1 /jan. 2011 124 4.1.2 ac and dc input levels for single-ended data signals table 29. single-ended ac and dc input levels for dq and dm symbol parameter 800mhz 900mhz/1.0ghz unit notes min max min max vih.dq(ac150) ac input logic high vref + 0.150 note 2 - - v 1, 2, 7 vil.dq(ac150) ac input logic low note 2 vref - 0.150 - - v 1, 2, 8 vih.dq(ac135) ac input logic high - - vref+0.135 note 2 mv 1, 2, 7 vil.dq(ac135) ac input logic lo w - - note 2 vref-0.135 mv 1, 2, 8 v refdq(dc ) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4 notes: 1. vref = vrefdq(dc). 2. see ?$paratext>? on page 135. 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. 5. vih(dc) is used as a simplif ied symbol for vih.dq(dc100) 6. vil(dc) is used as a simp lified symbol for vil.dq(dc100) 7. vih(ac) is used as a simplified symbol for vih. dq(ac175), vih.dq(ac150), and vih.dq(ac135); vih.dq(ac175) value is used when vref+0.175v is referenced, vih.dq(ac150) value is used when vref+0.150v is referenced, and vih.dq(ac135) va lue is used when vref+0.135v is referenced. 8. vil(ac) is used as a simplified symbol for vi l.dq(ac175), vil.dq(ac1 50), and vil.dq(ac135); vil.dq(ac175) value is used when vref-0.175v is referenced, vil.dq(ac150) value is used when vref-0.150v is referenced, and vil.dq(ac135) value is used when vref-0.135v is referenced
rev. 1.1 /jan. 2011 125 4.2 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and v refdq are illustrated in below figure 89. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g., 1 sec). this average has to meet the min/max requirements in table 34. furthermore v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. figure 89. illustration of v ref(dc) tolerance and v ref ac-noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are dependent on v ref . ?v ref ? shall be understood as v ref(dc) , as defined in figure 89. this clarifies that dc-variations of v ref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup an d hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram set up/hold specification and derating va lues need to include time and volt- age associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (+/- 1% of vdd) are included in dram timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 1.1 /jan. 2011 126 4.3 ac and dc logic input levels for differential signals 4.3.1 differential signal definition figure 90. definition of differential ac-swing and ?time above ac-level? t dvac 4.3.2 differential swing re quirements for clock (ck - ck ) and strobe (dqs-dqs ) time differential input voltage(i.e.dqs - dqs#, ck - ck#) v il.diff.ac.max v il.diff.max 0 v ih.diff.min v ih.diff.ac.min t dvac half cycle t dvac table 30. differential ac and dc input levels symbol parameter 800mhz/900mhz/1.0ghz unit notes min max vihdiff differential input high + 0.200 note 3 v 1 vildiff differential input logic low note 3 - 0.200 v 1 vihdiff(ac) differential input high ac 2 x (vih(ac) - vref) note 3 v 2 vildiff(ac) differential input low ac note 3 2 x (vil(ac) - vref) v 2 notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs , dqsl, dqsl , dqsu, dqsu use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to ?$paratext>? on page 135.
rev. 1.1 /jan. 2011 127 4.3.3 single-ended requireme nts for differential signals each individual component of a differe ntial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , of dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax ( approximately equal to the ac-levels (vih (ac) / vil (ac) for add/cmd si gnals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (appr oximately the ac-levels (vih (ac) / vil (ac)) for dq signals) in every half-cycle preceding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g., if vih.ca(ac150)/vil.ca(ac150) is used for add/cmd signals, then these ac -levels apply also for the single- ended signals ck and ck . table 31. allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 -
rev. 1.1 /jan. 2011 128 figure 91. single-ended requireme nt for differential signals. note that, while add/cmd and dq signal requirements are with respect to vref, the single-ended compo- nents of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the tran- sition of single-ended signals thr ough the ac-levels is used to m easure setup time. for single-ended components of differential signals the requir ement to reach vselmax, vsehmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. vdd or vddq vsehmin vdd/2 or vddq/2 vseh vselmax vss or vssq ck or dqs vsel time table 32. single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu symbol parameter 800mhz/900mhz/1.0ghz unit notes min max vseh single-ended high level for strobes (vdd / 2) + 0.175 note 3 v 1, 2 single-ended high level for ck, ck (vdd / 2) + 0.175 note 3 v 1, 2 vsel single-ended low level for strobes note 3 (vdd / 2) -0.175 v 1, 2 single-ended low level for ck, ck note 3 (vdd / 2) -0.175 v 1, 2 notes: 1. for ck, ck use vih/vil (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac- high or ac-low level is used for a signal group, then the reduced level applies also here 3. these values are not defined, howe ver the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to ?$paratext>? on page 135.
rev. 1.1 /jan. 2011 129 4.4 differential input cross point voltage to guarantee tight setup and hold times as well as outp ut skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in table 33. the differential input cross point voltage vix is measured from the actual cross point of true and complement signals to the mi dlevel between of vdd and vss. figure 92. vix definition 4.5 slew rate definitions for single-ended input signals see ?$paratext>? on page 159 for single-ended slew rate definitions for address and command signals. see ?$paratext>? on page 166 for single-ended slew rate definitions for data signals. 4.6 slew rate definitions for differential input signals vdd vss vdd/2 v ix v ix v ix ck , dqs ck, dqs table 33. cross point voltage for di fferential input signals (ck, dqs) symbol parameter 800mhz/900mhz/1.0ghz unit notes min max v ix differential input cross point voltage relative to vdd/2 for ck, ck - 150 150 mv - 175 175 mv 1 v ix differential input cross point voltage relative to vdd/2 for dqs, dqs - 150 150 mv notes: 1. extended range for v ix is only allowed for clock and if single-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/ -250 mv, and when the differential slew rate of ck - ck is larger than 3 v/ns. refer to table 32 on page 128 for vsel and vseh standard values.
rev. 1.1 /jan. 2011 130 input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in table 34 and figure 93. figure 93. differential input slew rate definition for dqs, dqs and ck, ck delta tfdiff delta trdiff v ih diffmin v il diffmax 0 differential input voltage (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck# table 34. differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin [vihdiffmi n - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff notes: 1. the differential signal (i.e., ck-ck and dqs-dqs ) must be linear between these thresholds.
rev. 1.1 /jan. 2011 131 5. ac & dc output measurement levels 5.1 single ended ac and dc output levels table 35 shows the output levels used for measurements of single ended signals. 5.2 differential ac and dc output levels table 36 shows the output levels used for measurements of differential signals. table 35. single-ended ac and dc output levels symbol parameter 800mhz/900mhz /1.0ghz unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol(dc) dc output low measurement level (for iv curve linearity) 0.2 x v ddq v v oh(ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol(ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 notes: 1. the swing of 0. 1 x v ddq is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2. table 36. differential ac and dc output levels symbol parameter 800mhz/900mhz /1.0ghz unit notes v ohdiff(ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v1 v oldiff(ac) ac differential output low measurement level (for output sr) - 0.2 x v ddq v1 notes: 1. the swing of 0.2 x v ddq is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2 at each of the differential outputs.
rev. 1.1 /jan. 2011 132 5.3 single ended output slew rate whit the reference load for timing measur ements, output slew rate for fallin g and rising edge s is defined and measured between v ol(ac) and v oh(ac) for single ended signals as shown in table 37 and figure 94. figure 94. single-ended output slew rate definition delta tfse delta trse v oh(ac) v ol(ac) v single ended output voltage(l.e.dq) table 38. output slew rate (single-ended) 800mhz 900mhz 1.0ghz units parameter symbol min max min max min max single-ended output slew rate srqse tbd 5 tbd 5 (1) tbd 5 (1) v/ns description: sr: slew rate q: query output (like in dq, whic h stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting notes: 1. in two cases, a maximum slew rate of 6v/ns applies for a single dq signal within a byte lane. case 1 is defined for a single dq signal within a byte lane wh ich is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e they stay at either high or low). case 2 in defined for a single dq signal within a byte lane whic h is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respective ly). for the remaining dq signa l switching into the opposite direction, the regular maximum limit of 5v/ns applies. table 37. single-ended outp ut slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) - v ol(ac) ] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) - v ol(ac) ] / deltatfse notes: 1. output slew rate is verified by design and characte rization, and may not be subject to production test.
rev. 1.1 /jan. 2011 133 5.4 differential output slew rate with the reference load for timing measur ements, output slew rate for fallin g and rising edge s is defined and measured between voldiff(ac) and vohd iff(ac) for differential signals as shown in table 39 and figure 95. figure 95. differential output slew rate definition delta tfdiff delta trdiff v ohdiff(ac) v oldiff(ac) o differential output voltage(i.e. dqs-dqs) table 39. differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff(ac) v ohdiff(ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff(ac) v oldiff(ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatfdiff notes: 1. output slew rate is verified by design and characte rization, and may not be subject to production test. table 40. differential output slew rate 800mhz 900mhz 1.0ghz units parameter symbol min max min max min max differential output slew rate srqdiff 5 10 5 12 5 12 v/ns description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differentialsignals for ron = rzq/7 setting
rev. 1.1 /jan. 2011 134 5.5 reference load for ac timing and output slew rate figure 96 represents the effective reference load of 25 ohms used in defining the relevant ac timing parame- ters of the device as well as output slew rate measurements. it is not intended as a precise representation of any partic ular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manu facturers correlate to their production test condi- tions, generally one or more coaxial transmissi on lines terminated at the tester electronics. figure 96. reference load for ac timing and output slew rate dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck
rev. 1.1 /jan. 2011 135 5.6 overshoot and unde rshoot specifications 5.6.1 address and control overshoo t and undershoot specifications figure 97. address and control overshoot and undershoot definition maximum amplitude overshoot area vdd vss maxim um am plitude undershoot area time (ns) volts (v) table 41. ac overshoot/undershoot specification for address and control pins parameter 800mhz 900mhz 1.0ghz units maximum peak amplitude allowed for overshoot area. (see figure 97) 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. (see figure 97) 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure 97) 0.33 0.28 0.25 v-ns maximum undershoot area below vss (see figure 97) 0.33 0.28 0.25 v-ns (a0-a15, ba0-ba3, cs , ras , cas , we , cke, odt)
rev. 1.1 /jan. 2011 136 5.6.2 clock, data , strobe and mask overshoot and unde rshoot specifications figure 98. clock, data, strobe and mask overshoot and undershoot definition maximum amplitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) volts (v) table 42. ac overshoot/undershoot specification for clock, data, strobe and mask parameter 800mhz 900mhz 1.0ghz units maximum peak amplitude allowed for overshoot area. (see figure 98) 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. (see figure 98) 0.4 0.4 0.4 v maximum overshoot area above vddq (see figure 98) 0.13 0.11 0.10 v-ns maximum undershoot area below vssq (see figure 98) 0.13 0.11 0.10 v-ns (ck, ck , dq, dqs, dqs , dm)
rev. 1.1 /jan. 2011 137 5.7 output driver dc electrical characteristics a functional representation of the output buffer is shown in figure 99. output driver impedance ron is defined by the value of the external reference resistor rzq as follows: ron 34 = r zq / 7 (nominal 34.3 ohm +/- 10% with nominal r zq = 240 ohm) the individual pull-up and pull-down resistors ( ron pu and ron pd ) are defined as follows: under the condition that ron pd is turned off under the condition that ron pu is turned off figure 99. output driver: definition of voltages and currents ron pu v ddq v out ? i out -------------------- ------------------ = ron pd v out i out -------------- - = to other circuitry like rcv, ... i pu ron pu ron pd i pd output driver i out v out vssq dq vddq chip in drive mode
rev. 1.1 /jan. 2011 138 table 43. output driver dc elec trical characteristics, assuming r zq = 240 ; entire operating temper- ature range; after proper zq calibration ron nom resistor v out min nom max unit notes 34 ron 34pd v oldc = 0.2 x v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 x v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 ron 34pu v oldc = 0.2 x v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 x v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 40 ron 40pd v oldc = 0.2 x v ddq 0.6 1.0 1.1 r zq /6 1, 2, 3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 r zq /6 1, 2, 3 v ohdc = 0.8 x v ddq 0.9 1.0 1.4 r zq /6 1, 2, 3 ron 40pu v oldc = 0.2 x v ddq 0.9 1.0 1.4 r zq /6 1, 2, 3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 r zq /6 1, 2, 3 v ohdc = 0.8 x v ddq 0.6 1.0 1.1 r zq /6 1, 2, 3 mismatch between pull-up and pull-down, mm pupd v omdc 0.5 x v ddq -10 +10 % 1, 2, 4 notes: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage cha nges after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specif ied under the condition that v ddq = v dd and that v ssq = v ss . 3. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x v ddq . other calibration schemes may be used to achieve the linear ity spec shown above, e. g. calibration at 0.2 x v ddq and 0.8 x v ddq . 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ron pu and ron pd , both at 0.5 * v ddq : mm pupd ron pu ron pd ? ron nom ---------------- ----------------- ---------------- x 100 =
rev. 1.1 /jan. 2011 139 5.7.1 output driver temper ature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table 44 and table 45. t = t - t(@calibration); v = vddq - vddq(@calibration); vdd = vddq note: dr on dt and dr on dv are not subject to production test bu t are verified by design and characteriza- tion. table 44. output driver sensitivity definition min max unit ronpu@ v ohdc 0.6 - dr on dth*| t| - dr on dvh*| v| 1.1 + dr on dth*| t| + dr on dvh*| v| rzq/7 ron@ v omdc 0.9 - dr on dtm*| t| - dr on dvm*| v| 1.1 + dr on dtm*| t| + dr on dvm*| v| rzq/7 ronpd@ v oldc 0.6 - dr on dtl*| t| - dr on dvl*| v| 1.1 + dr on dtl*| t| + dr on dvl*| v| rzq/7 table 45. output driver voltage and temperature sensitivity speed bin 800mhz 900mhz/1.0ghz units min max min max dr on dtm 01.501.5 %/ o c dr on dvm 0 0.15 0 0.13 %/mv dr on dtl 01.501.5 %/ o c dr on dvl 0 0.15 0 0.13 %/mv dr on dth 01.501.5 %/ o c dr on dvh 0 0.15 0 0.13 %/mv these parameters may not be subject to production test . they are verified by design and characterization.
rev. 1.1 /jan. 2011 140 5.8 on-die termination (odt) levels and i-v characteristics 5.8.1 on-die termination (odt) le vels and i-v characteristics on-die termination effective resist ance rtt is defined by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs and tdqs/tdqs (x8 devices only) pins. a functional representation of the on-die termination is shown in figure 100. the individual pull-up and pull- down resistors ( rtt pu and rtt pd ) are defined as follows: under the condition that rtt pd is turned off under the condition that rtt pu is turned off figure 100. on-die termination: definition of voltages and currents rtt pu v ddq v out ? i out ------------------- -------------- = rtt pd v out i out ------------ - = to other circuitry like rcv, ... i pu rtt pu rtt pd i pd odt iout v out vssq dq vddq chip in termination mode i out = i pd - i pu io_ctt_definition_01
rev. 1.1 /jan. 2011 141 5.8.2 odt dc electri cal characteristics table 46 provides an overview of the odt dc electrical characteristics. the values for rtt 60pd120 , rtt 60pu120 , rtt 120pd240 , rtt 120pu240 , rtt 40pd80 , rtt 40pu80 , rtt 30pd60 , rtt 30pu60 , rtt 20pd40 , rtt 20pu40 are not specification requirements, bu t can be used as design guide lines: table 46. odt dc electrical characteristics, assuming r zq = 240 +/-1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes 0, 1, 0 120 rtt 120pd240 v oldc 0.2 v ddq 0.61.001.1 r zq 1,2,3,4 0.5 v ddq 0.91.001.1 r zq 1,2,3,4 v ohdc 0.8 v ddq 0.91.001.4 r zq 1,2,3,4 rtt 120pu240 v oldc 0.2 v ddq 0.91.001.4 r zq 1,2,3,4 0.5 v ddq 0.91.001.1 r zq 1,2,3,4 v ohdc 0.8 v ddq 0.61.001.1 r zq 1,2,3,4 rtt 120 v il(ac) to v ih(ac) 0.91.001.6 r zq /2 1,2,5 0, 0, 1 60 rtt 60pd120 v oldc 0.2 v ddq 0.61.001.1 r zq /2 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /2 1,2,3,4 v ohdc 0.8 v ddq 0.91.001.4 r zq /2 1,2,3,4 rtt 60pu120 v oldc 0.2 v ddq 0.91.001.4 r zq /2 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /2 1,2,3,4 v ohdc 0.8 v ddq 0.61.001.1 r zq /2 1,2,3,4 rtt 60 v il(ac) to v ih(ac) 0.91.001.6 r zq /4 1,2,5 0, 1, 1 40 rtt 40pd80 v oldc 0.2 v ddq 0.61.001.1 r zq /3 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /3 1,2,3,4 v ohdc 0.8 v ddq 0.91.001.4 r zq /3 1,2,3,4 rtt 40pu80 v oldc 0.2 v ddq 0.91.001.4 r zq /3 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /3 1,2,3,4 v ohdc 0.8 v ddq 0.61.001.1 r zq /3 1,2,3,4 rtt 40 v il(ac) to v ih(ac) 0.91.001.6 r zq /6 1,2,5
rev. 1.1 /jan. 2011 142 table 46. odt dc electrical characteristics, assuming r zq = 240 +/-1% entire operating temperature range; after proper zq calibration (cont?d) mr1 a9, a6, a2 rtt resistor v out min nom max unit notes 1, 0, 1 30 rtt 30pd60 v oldc 0.2 v ddq 0.61.001.1 r zq /4 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /4 1,2,3,4 v ohdc 0.8 v ddq 0.91.001.4 r zq /4 1,2,3,4 rtt 30pu60 v oldc 0.2 v ddq 0.91.001.4 r zq /4 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /4 1,2,3,4 v ohdc 0.8 v ddq 0.61.001.1 r zq /4 1,2,3,4 rtt 30 v il(ac) to v ih(ac) 0.91.001.6 r zq /8 1,2,5 1, 0, 0 20 rtt 20pd40 v oldc 0.2 v ddq 0.61.001.1 r zq /6 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /6 1,2,3,4 v ohdc 0.8 v ddq 0.91.001.4 r zq /6 1,2,3,4 rtt 20pu40 v oldc 0.2 v ddq 0.91.001.4 r zq /6 1,2,3,4 0.5 v ddq 0.91.001.1 r zq /6 1,2,3,4 v ohdc 0.8 v ddq 0.61.001.1 r zq /6 1,2,3,4 rtt 20 v il(ac) to v ih(ac) 0.91.001.6 r zq /12 1,2,5 deviation of v m w.r.t. v ddq /2, d v m -5 +5 % 1,2,5,6 notes: 1. the tolerance limits are specified after calibration with stab le voltage and temperature. for the behavior of the toler- ance limits if temperature or voltage changes after calibra tion, see following section on voltage and temperature sen- sitivity. 2. the tolerance limits are spec ified under the condition that v ddq = v dd and that v ssq = v ss . 3. pull-down and pull-up odt resistors are recommended to be calibrated at 0.5 x v ddq . other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x v ddq and 0.8 x v ddq . 4. not a specification requirement, but a design guide line. 5. measurement definition for rtt : apply v ih(ac) to pin under test and measure current i ( v ih(ac) ), then apply v il(ac) to pin under test and measure current i ( v il(ac) ) respectively. measurement definition for v m and d v m : measure voltage ( v m ) at test pin (midpoint) with no lo ad: rtt v ih(ac) v il(ac) ? i (vih(ac)) i (vil(ac)) ? ---------------------------------- ----------------------- = v m 2 v m ? v ddq ----------------- -1 ? ?? ?? 100 ? =
rev. 1.1 /jan. 2011 143 5.8.3 odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table 47 and table 48. dt = t - t(@calibration); dv=vdd q - vddq(@calibration); vdd = vddq these parameters may not be subject to production te st. they are verified by design and characterization. 5.9 odt timing definitions 5.9.1 test load for odt timings different than for timing measurem ents, the reference load for odt timings is defined in figure 101. figure 101. odt timing reference load bd_refload_odt ck ck, vddq dqs dqs, tdqs tdqs, dq, dm dut vtt = vssq rtt = 25 vssq timing reference points table 47. odt sensitivity definition min max unit rtt 0.9 - dr tt dt*| t| - dr tt dv*| v| 1.6 + dr tt dt*| t| + dr tt dv*| v| rzq/2,4,6,8,12 table 48. odt voltage and temperature sensitivity min max unit dr tt dt 0 1.5 %/ o c dr tt dv 0 0.15 %/mv
rev. 1.1 /jan. 2011 144 5.9.2 odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd and t adc are provided in table 49 and subsequent figures. mea- surement reference settings are provided in table 50. table 49. odt ti ming definitions symbol begin point definition end point definition figure t aon rising edge of ck - ck defined by the end point of odtlon extrapolated point at vssq figure 102 t aonpd rising edge of ck - ck with odt being first registered high extrapolated point at vssq figure 103 t aof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure 104 t aofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom figure 105 t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure 106 table 50. reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq /12 r zq /2 0.20 0.30
rev. 1.1 /jan. 2011 145 figure 102. definition of t aon figure 103. definition of t aonpd t aon t sw1 t sw2 v sw1 v sw2 begin point: rising edge of ck ? ck defined by the end point of odtlon ck ck dq, dm dqs, dqs tdqs, tdqs vssq end point: extrapolated point at vssq vssq vtt t aonpd t sw1 t sw2 v sw1 v sw2 begin point: rising edge of ck ? ck with odt being first registered high ck ck dq, dm dqs, dqs tdqs, tdqs vssq end point: extrapolated point at vssq vssq vtt
rev. 1.1 /jan. 2011 146 figure 104. definition of t aof figure 105. definition of t aofpd t aof v sw2 begin point: rising edge of ck ? ck defined by the end point of odtloff ck ck dq, dm dqs, dqs tdqs, tdqs end point: extrapolated point at vrtt_nom vssq vtt t sw1 t sw2 v sw1 vrtt_nom t aofpd v sw2 begin point: rising edge of ck ? ck with odt being first registered low ck ck dq, dm dqs, dqs tdqs, tdqs end point: extrapolated point at vrtt_nom vssq vtt t sw1 t sw2 v sw1 vrtt_nom
rev. 1.1 /jan. 2011 147 figure 106. definition of t adc t adc v sw2 begin point: rising edge of ck ? ck defined by the end point of odtlcnw ck ck dq, dm dqs, dqs tdqs, tdqs end point: extrapolated point at vrtt_nom vtt t sw11 t sw21 vrtt_nom t adc t sw12 t sw22 v sw1 vrtt_nom begin point: rising edge of ck ? ck defined by the end point of odtlcwn4 or odtlcwn8 vrtt_wr vssq
rev. 1.1 /jan. 2011 148 tck ( avg ) = ? tck j ? / n j = 1 n n = 200 where 6. electrical characteristi cs & ac timing for 800mhz to 1.0ghz 6.1 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max val- ues may result in malfunction of the ddr3 sdram device. 6.1.1 definition for tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. 6.1.2 definition for tck(abs) tck(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tck(abs) is not subject to production test. 6.1.3 definition for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. tch ( avg ) = ? tch j ? / (n x tck(avg)) j = 1 n n = 200 where tcl ( avg ) = ? tcl j ? / (n x tck(avg)) j = 1 n n = 200 where
rev. 1.1 /jan. 2011 149 6.1.4 definition for tj it(per) and tjit(per,lck) tjit(per) = min/max of {tck i = tck(avg) where i = 1 to 200}. tjit(per) is defined as the largest devi ation of any signal tck from tck(avg). tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not subject to production test. 6.1.5 definition for tj it(cc) and tjit(cc,lck) tjit(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. tjit(cc) = max of |{tck i + 1 - tck i }|. tjit(cc) defines the cycle to cycle jitte r when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit (cc,lck) are not subject to production test. 6.1.6 definition for terr(nper) terr is defined as the cumulative error across n mult iple consecutive cycles from tck(avg). terr is not sub- ject to production test. 6.2 refresh parameters by device density table 51. refresh parameters by device density notes: 1. users should refer to the dram supplier data sheet an d/or the dimm spd to determine if ddr3 sdram devices support the following options or requirements referred to in this material. parameter rtt_nom setting 1gb units notes ref command to act or ref command time trfc 110 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 us 85 c < t case 95 c 3.9 us 1
rev. 1.1 /jan. 2011 150 7. electrical character istics and ac timing 7.1 timing parameters for 800mhz , 900mhz, and 1.0ghz speed bins table 52. timing parameters by speed bin note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8-8-8-ns6 average clock period tck (avg) see ?10. standard speed bins? on page 62. ps f average high pulse width tch (avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) f average low pulse width tcl (avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) f absolute clock period tck (abs) tck(avg)min+tjit(per)min ps absolute clock high pulse width tch (abs) 0.43 - 0.43 - 0.43 - tck (avg) 25 absolute clock low pulse width tcl (abs) 0.43 - 0.43 - 0.43 - tck (avg) 26 clock period jitter jit (per) -70 70 -60 60 -40 40 ps clock period jitter during dll locking period tjit (per, lck) -6060-5050-3030ps cycle to cycle period jitter tjit (cc) 140 140 130 130 tbd tbd ps cycle to cycle period jitter during dll locking period tjit (cc, lck) 120 120 110 110 tbd tbd ps duty cycle jitter tjit (duty) ----tbdtbdps cumulative error across 2 cycles terr (2per) -103 103 -93 93 tbd tbd ps cumulative error across 3 cycles terr (3per) -122 122 -112 112 tbd tbd ps cumulative error across 4 cycles terr (4per) -136 136 -122 122 tbd tbd ps cumulative error across 5 cycles terr (5per) -147 147 -135 135 tbd tbd ps cumulative error across 6 cycles terr (6per) -155 155 -140 140 tbd tbd ps cumulative error across 7 cycles terr (7per) -163 163 -146 146 tbd tbd ps cumulative error across 8 cycles terr (8per) -169 169 -149 149 tbd tbd ps cumulative error across 9 cycles terr (9per) -175 175 -160 160 tbd tbd ps
rev. 1.1 /jan. 2011 151 cumulative error across 10 cycles terr (10per) -180 180 -165 165 tbd tbd ps cumulative error across 11 cycles terr (11per) -184 184 -168 168 tbd tbd ps cumulative error across 12 cycles terr (12per) -188 188 -170 170 tbd tbd ps cumulative error across n = 13, 14,.....49, 50 cycles terr (nper) terr(nper)min=(1+0.68ln(n))*jit(per)min terr(nper)max=(1+0.68ln(n))*jit(per)max ps 24 data timing dqs, dqs to dq skew, per group, per access tdqsq 100 - 87 - 75 - ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - 0.38 - tck (avg) 13, b dq low-impedance time from ck, ck tlz (dq) -450 225 -400 200 -360 180 ps 13, 14, a dq high impedance time from ck, ck thz (dq) - 225 - 200 - 180 ps 13, 14, a data setup time to dqs, dqs referenced to vih (ac) / vil (ac) levels tds (base) 10 - 0 - -10 - ps d, 17 data hold time from dqs, dqs referenced to vih (dc) / vil (dc) levels tdh (base) 45 - 45 - 40 - ps d, 17 data strobe timing dqs,dqs differential read preamble trpre 0.9 note 0.9 note 0.9 tbd tck (avg) 13, 19 b dqs, dqs differential read postamble trpst 0.3 note 0.3 note 0.3 tbd tck (avg) 11, 13, b dqs, dqs differential output high time tqsh 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential output low time tqsl 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential write preamble twpre 0.9 - 0.9 - 0.9 - tck (avg) dqs, dqs differential write postamble twpst 0.3 - 0.3 - 0.3 - tck (avg) dqs, dqs rising edge output access time from rising ck, ck tdqsck -225 225 -180 180 -180 180 ps 13, a dqs and dqs low- impedance time (referenced from rl - 1) tlz(dqs) -450 225 -400 200 -360 180 ps 13, 14, a dqs and dqs high- impedance time (referenced from rl + bl/2) thz(dqs) -225-200-180ps 13, 14 a table 52. timing parameters by speed bin (continued) note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes
rev. 1.1 /jan. 2011 152 dqs, dqs differential input low pulse width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs differential input high pulse width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs rising edge to ck, ck rising edge tdqss -0.25 0.25 -0.25 0.25 -0.3 0.3 tck (avg) c dqs, dqs falling edge setup time to ck, ck rising edge tdss 0.2 - 0.2 - 0.2 - tck (avg) c dqs, dqs falling edge hold time from ck, ck rising edge tdsh 0.2 - 0.2 - 0.2 - tck (avg) c command and address timing dll locking time tdllk 512 - 512 - 512 - nck internal read command to precharge command delay trtp max(4nc k, 7.5ns) - max(4nc k, 7.5ns) - max(4nc k, 7.5ns) -e delay from start of internal write transaction to internal read command twtr max(4nc k, 7.5ns) - max(4nc k, 7.5ns) - max(4nc k, 7.5ns) -e, 18 write recovery time twr 16.3 - 15.6 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - 4 - nck mode register set command update delay tmod max(12nc k,15ns) - max(12nc k,15ns) - max(12n ck,15ns - act to internal read or write delay time trcd 15 - 15.4 - 16 - e pre command period trp 15 - 15.4 - 16 - e act to act or ref command period trc 50 - 50.6 - 52 - e cas to cas command delay tccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal (min) 24 - 28 - 31 - nck end of mpr read burst to msr for mpr (exit) tmprr 1 - 1 - 1 - nck 22 active to precharge command period tras 37.5 - 37.4 - 37 - e active to active command period for 2kb page size trrd 7 - 7 - 7 - e table 52. timing parameters by speed bin (continued) note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes
rev. 1.1 /jan. 2011 153 four activate window for 2kb page size tfaw 42.5 - 41.8 - 40 - ns e command and address setup time to ck, ck referenced to vih (ac) / vil (ac) levels tis (base) 45 - 35 25 - ps b, 16 command and address hold time from ck, ck referenced to vih (dc) / vil (dc) levels tih (base) 120 - 110 - 100 - ps b, 16 calibration timing - power-up and reset calibration time tzqinit 512 - 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max(5nsc k, trfc(min )+10ns) - max(5nsc k, trfc(min )+10ns) - max(5ns ck, trfc(mi n)+10ns) - self refresh timings exit self refresh to commands not requiring a locked dll txs max(5nsc k, trfc(min )+10ns) - max(5nsc k, trfc(min )+10ns) - max(5ns ck, trfc(mi n)+10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(mi n) - tdllk(mi n) - tdllk(mi n) -nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min)+1nck tcke(min)+1nck tcke(mi n)+1nck - valid clock requirement after self refresh entry (sre) or power-down entry (pde) tcksre max(5nsc k, 10ns) - max(5nsc k, 10ns) - max(5ns ck, 10ns) - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit tcksrx max(5nsc k, 10ns) - max(5nsc k, 10ns) - max(5ns ck, 10ns) - power down timings table 52. timing parameters by speed bin (continued) note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes
rev. 1.1 /jan. 2011 154 exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp 7 - 7 - 7 - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max(10n ck,24ns) - max(10n ck,24ns) - max(10n ck,24ns) -2 cke minimum pulse width tcke 4 - 5 - 5 - command pass disable delay tcpded 1 - 1 - 1 - nck power down entry to exit timing tpd tcke(min ) 9*tre fi tcke(min ) 9*tre fi tcke(mi n) 9*tre fi 15 timing of act command to power down entry tactpden 1 - 1 - 1 - nck timing of pre or prea command to power down entry tprpden 1 - 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl+4+1 - rl+4+1 - rl+4+1 - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl+4+(t wr/tck(a vg)) - wl+4+(t wr/tck(a vg)) - wl+4+(t wr/tck( avg)) -nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl+4+w r+1 - wl+4+w r+1 - wl+4+w r+1 -nck10 timing of wr command to power down entry (bc4mrs) twrpden wl+2+(t wr/tck(a vg)) - wl+2+(t wr/tck(a vg)) - wl+2+(t wr/tck( avg)) -nck 9 timing of wra command to power down entry (bc4mrs) twrapden wl+2+w r+1 - wl+2+w r+1 - wl+2+w r+1 -nck10 timing of ref command to power down entry trefpden 1 - 1 - 1 - nck , timing of mrs command to power down entry tmrspden tmod(min ) - tmod(min ) - tmod(mi n) - odt timings odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - nck table 52. timing parameters by speed bin (continued) note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes
rev. 1.1 /jan. 2011 155 odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt turn- on delay (power-down with dll frozen) taonpd 191919ns asynchronous rtt turn- off delay (power-down with dll frozen) taofpd 1 9 1 9 1 9 ns rtt turn-on taon -225 225 -200 200 -175 175 ps 7, a rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) 8, a rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) a write leveling timings first dqs/dqs rising edge after write leveling mode is programmed twlmrd 40 - 40 - 40 - nck 3 dqs/dqs delay after write leveling mode is programmed twldqsen 25 - 25 - 25 - nck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 170 - 130 - 120 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 170 - 130 - 120 - ps write leveling output delay twlo 090909ns write leveling output error twloe 0 2 0 2 0 2 ns table 52. timing parameters by speed bin (continued) note: the following general notes from page 156 appl y to table 52: note a. vdd=vddq=1.5v+/-0.075v 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes
rev. 1.1 /jan. 2011 156 7.2 jitter notes a. until ?tck (avg)? represents the actual tck (avg) of the input clock under operation. unit ?nck? repre- sents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd = 4[nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x tck (avg) + terr(4per), min. b. these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit (per), tjit (cc) , etc.), as the setup and hold are relative to the clock signal crossing t hat latches the command/address. that is, these parameters should be met whether clock jitter is present or not. c. these parameters are measured from a data strobe signal (dqs(l/u), dqs(l/u) ) crossing to its respective clock signal (ck, ck ) crossing. the spec values are no t affected by the amount of clock jitter applied (i.e. tjit (per), tjit (cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. d. these parameters are measured from a data sign al (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u), dqs (l/u)) crossing. e. for these parameters, the ddr3 sdram device supports tnparam [nck] = ru {tparam [ns] / tck (avg) [ns]}, which is in clock cyc les, assuming all inpu t clock jitter specifications are satisfied.for example, the device will support tnrp = ru {trp / tc k (avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, the device will support tnrp = ru {trp / tck (avg)} = 6, as long as the input clock jitter specifications are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. f. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr (mper), act of the input clock, where 2 <= m <=12.(output deratings ar e relative to the sdram input clock.) for example, if the measured jitter into a ddr-8 00 sdram has terr (mper), act, min = -172 ps and terr (mper), act, max =+ 193 ps, then t dqsck, min (derated) = tdqsck, min - terr (mper), act, max = -400 ps - 193 ps = - 593 ps and tdqsck, max (derated) = tdqsck, max - terr (mper), act, min = 400 ps+ 172 ps = + 572 ps. similarly, tlz (dq) for ddr3-800 derates to tlz (dq), min (derated) = - 800 ps - 193 ps = - 993 ps and tlz (dq), max (derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr (mper), act, min is the minimum measured value of terr (nper) where 2 <= n <=12, and terr (mper), act, max is the maximum meas ured value of terr (nper) where 2 <= n <= 12 g. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit (per), act of the input clock. (output deratings are relative to the sdram input clock.) for exam- ple, if the measured jitter into a ddr3-800 sdram has tck (avg), act = 2500 ps, tjit (per), act, min = - 72 ps and tjit (per), act, max = + 93 ps, then tr pre, min (derated) = trpre, min + tjit (per), act, min = 0.9 x tck (avg), act + tjit (per), act + tjit (per), act, min = 0.9 x 2500 ps - 72 ps =+ 2178 ps. similarly, tqh, min (derated) = tqh, min + tjit (per), act, min = 0.38 x tck (avg), act + tjit (per), act, min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!)
rev. 1.1 /jan. 2011 157 7.3 timing parameter notes 1. a ctual value dependant upon measurement level definitions see ?$paratext>? on page 87 and see ?$paratext>? on page 87. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rounded-up to next higher integer value. 6. there is no maximum cycle time limit besides th e need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see ?$paratext>? on page 109. 8. for definition of rtt turn-off time taof see ?$paratext>? on page 109. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0. 11. the maximum read postamble is bound by thzdqs(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. see ?$paratext>? on page 76. 12. output timing deratings are relative to the sdram input clo ck. when the device is operated with input clock jitter, this parameter needs to be derated by t.b.d. 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter for definition and measurement method. 15. trefi depends on toper 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset , vref(dc) = vre- fca(dc). see ?$paratext>? on page 159. 17. tds(base) and tdh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset , vref(dc) = vre- fca(dc). see ?$paratext>? on page 166. 18. start of internal write tran saction is defined as follows: for bl8 (fixed by mrs and on- the-fly): rising clock edge 4 clock cycles after wl. for bc4 (on- the- fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum read preamble is bound by tlz(dqs)min on the left side and tdqsck(max) on the right side.see ?$paratext>? on page 76. 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see ?$paratext>? on page 104. 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5% (zq correction) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensit ivities specified in the ?out put driver voltage and tem- perature sensitivity? and ?odt voltage and temperature sensitivity? tables. t he appropriate interval between zqcs commands can be determined from these tables and other application-specific parameters. one method for calculating the interval between zqcs comm ands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that t he sdram is subject to in the application, is illustrated. the interval could be defined by the following formula:
rev. 1.1 /jan. 2011 158 where tsens = max(drttdt, drondtm) and vsens = max( drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / o c, vsens = 0.15% / mv, tdriftrate = 1 o c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse wid th, as measured from one rising edge to the following fall- ing edge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following ris- ing edge. 27. the tis(base) ac150 specificat ions are adjusted from the tis(base) specif ication by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account for the earlier ref- erence point [(175 mv - 150 mv) / 1 v/ns]. 28. pulse width of a input signal is defined as the width betwe en the first crossing of vref(d c) and the consecutive cross- ing of vref(dc). 29. tdqsl describes the instantaneous differ ential input low pulse width on dqs - dqs , as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs - dqs , as measured from one rising edge to the next consecutive falling edge. 31. tdqsh,act + tdqsl,act = 1 tck,act; with txyz,act being the actual measured value of the respective timing parame- ter in the application. 32. tdsh,act + tdss,act = 1 tck,act; with txyz,act being the ac tual measured value of the respective timing parameter in the application. zqcorrection (tsens x tdriftrate)+ ( vsens x vdriftrate) -------------------------- ------------------------------ ----------------------------- ----------------------- 0.5 (1.5 x 1)+(0.15 x 15) --------------------------- --------------------------- 0 . 1 3 3 1 2 8 m s =
rev. 1.1 /jan. 2011 159 7.4 address / command se tup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calc ulated by adding the data sheet tis(base) and tih(base) value (see table 53) to the tis and tih derating value (see table 54) respec- tively. example: tis (total setup time) = tis(base) + tis setup (tis) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value (see figure 107). if the actual signal is later than the nominal sl ew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to v ref(dc) level is used for derating value (see figure 109). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref(dc) . hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref(dc) region?. use nominal slew rate for derating value (see figure 108). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 110). for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac (see table 58). although for slow slew rates the to tal setup time might be negative (i.e . a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition, a va lid input signal is still re quired to complete the transition and reach v ih/il(ac) . for slew rate in between the values listed in table 59 , the derating values may obtained by linear interpola- tion. these values are typically not subject to production te st. they are verified by design and characterization. table 53. add/cmd setup and ho ld base-values for 1v/ns not es: 1. (ac/dc referenced for 1v/ns address/comman d slew rate and 2 v/ns differential ck-ck slew rate) 2. the tis(base) ac150 specifications are adjusted from the ti s(base) ac175 specification by adding an additional 125 ps for 800mhz of derating to accommodate for the lowe r alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns. symbol reference 800mhz 900mhz 1.0ghz units tis(base) ac175 v ih/l(ac) 45 35 tbd ps tis(base) ac150 v ih/l(ac) 170 160 tbd ps tih(base) dc100 v ih/l(dc) 120 110 tbd ps
rev. 1.1 /jan. 2011 160 table 55. derating values 800mhz tist/ih - ac/dc based - alternate ac150 threshold tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac) = vref(dc)+150mv, vil(ac) = vref(dc)-150mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/ add slew rate v/ns 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 1612242032304046 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0-160-160-168 -816 0 24 8 32184034 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 table 54. derating values 800mhz tis/tih - ac/dc based ac175 threshold tis, tih derating in [ps] ac/dc based ac175 threshold -> vih(ac) = vref(d c)+175mv, vil(ac) = vref(dc)-175mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/ add slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10
rev. 1.1 /jan. 2011 161 table 56. required time t avc above vih(ac) {below vil(ac)} for valid add/cmd transition slew rate [v/ns] t vac @ 175 mv [ps] t vac @ 150 mv [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 -
rev. 1.1 /jan. 2011 162 figure 107. illustration of nominal slew rate and t vac for setup time t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tih tis tih tis ck ck
rev. 1.1 /jan. 2011 163 figure 108. illustration of nomi nal slew rate for hole time t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region ck ck tis tih tis tih
rev. 1.1 /jan. 2011 164 figure 109. illustration of tangent line for setup time t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr tangent line [ v ref(dc) - v il(ac) max] tf = tangent line [v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac ck ck tis tih tis tih
rev. 1.1 /jan. 2011 165 figure 110. illustration of tangent line for setup time t ih (for add/cmd with respect to clock). v ss hold slew rate tf tr tangent line [v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] tr = rising signal ck tis tih tis tih ck
rev. 1.1 /jan. 2011 166 7.5 data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 57) to the tds and tdh (see table 58) derating value respectively. example: tds (tot al setup time) = tds(base) + tds. setup (tds) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tds) nom inal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac) max (see figure 111). if the actual signal is always earlier than th e nominal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to v ref(dc) level is used for derating value (see figure 113). hold (tdh) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc) min and the first crossing of v ref(dc) (see figure 112). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 114). for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac (see table 60). although for slow slew rates the to tal setup time might be negative (i.e . a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a va lid input signal is still required to co mplete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpola- tion. these values are typically not subject to production te st. they are verified by design and characterization. table 57. data setup and hold base-values not es: 1. (ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) symbol reference 800mhz 900mhz 1.0ghz units tds(base) ac175 v ih/l(ac) ---ps tds(base) ac150 v ih/l(ac) 10 - - ps tdh(base) dc100 v ih/l(dc) 45 45 tbd ps
rev. 1.1 /jan. 2011 167 table 58. derating values (ac175) not es: 1. cell contents shaded in red are defined as ?not supported?. tds, tdh derating in [ps] ac/dc based 1 dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1.0 000000881616 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1-107 -21582324 0.5 - - - - - - - - - --11-16-2-6 510 0.4 - - - - - - - - - - - - -30 -26 -22 -10 table 59. derating values for (ac150) derating not es: 1. cell contents shaded in red are defined as ?not supported?. tds, tdh derating in [ps] ac/dc based 1 dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 75 50 75 50 75 50 - - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1.0 000000881616 - - - - - - 0.9 - - 0 -4 0 -4 8 4 16122420 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24143224 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 -16 22 -6 30 10 0.4 - - - - - - - - - - - - 7 -2615-10
rev. 1.1 /jan. 2011 168 table 60. required time t avc above vih(ac) {below vil(ac)} for valid dq transition slew rate [v/ns] 800mhz (ac175) 800mhz (ac150) 900mhz/1.0ghz t vac [ps] t vac [ps] t vac [ps] min max min max min max > 2.0 75 - 175 - tbd - 2.0 57 - 170 - tbd - 1.5 50 - 167 - tbd - 1.0 38 - 163 - tbd - 0.9 34 - 162 - tbd - 0.8 29 - 161 - tbd - 0.7 22 - 159 - tbd - 0.6 13 - 155 - tbd - 0.5 0 - 155 - tbd - < 0.5 0 - 150 - tbd -
rev. 1.1 /jan. 2011 169 figure 111. illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds
rev. 1.1 /jan. 2011 170 figure 112. illustration of nominal slew rate for hold time t dh (for dq with respect to strobe) v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds
rev. 1.1 /jan. 2011 171 figure 113. illustration of tangent line for setup time t ds (for dq with respect to strobe) v ss tdh setup slew rate setup slew rate rising signal falling signal tf tr tangent line [ v ref(dc) - v il(ac) max] tf = tangent line [v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds
rev. 1.1 /jan. 2011 172 figure 114. illustration of tangent line for hold time t dh (for dq with respect to strobe) v ss hold slew rate tf tr tangent line [v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] tr = rising signal tdh tds dqs dqs tdh tds

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